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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2017-11-06
14:55		 Kumamoto Kumamoto-Kenminkouryukan Parea An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics) VLD2017-36 DC2017-42		 Today, semiconductor technologies have developed and advance the integration density of LSI circuits.
A technique which... [more]		 VLD2017-36 DC2017-42
pp.55-60
DC 2017-02-21
12:00		 Tokyo Kikai-Shinko-Kaikan Bldg. An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77		 Today, advancements of semiconductor technology have progress to high integration of LSI circuits.
A technique which ke... [more]		 DC2016-77
pp.17-22
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