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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CAS, MSS, SIP 2016-06-17
16:10
Aomori Hirosaki Shiritsu Kanko-kan Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements
Daiki Toyoshima, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34
Asynchronous bundled-data transfer circuits use delay elements as a strobe signal which indicates the stable state of th... [more] CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34
pp.185-190
DC 2015-06-16
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. A Study on Function Test of Latch-based Asynchronous Pipeline Circuits
Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] DC2015-19
pp.19-24
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