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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2016-04-14 10:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 7T-SRAM with Data-Write Technique by Capacitive Coupling Daisaburo Takashima, Masato Endo (Toshiba), Kazuhiro Shimazaki, Manabu Sai (Toshiba Microelectronics), Masaaki Tanino (Toshia Information Systems)  ICD2016-2 |
A 7T-SRAM, in which cell data is written by capacitive coupling, is proposed. The elimination of current-drive in read/w... [more] | ICD2016-2 pp.7-12 |
| ICD | 2011-04-18 10:50 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
A Technical Trend and Embedded DRAM Technology for High-Performance NAND Flash Memories Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii (Toshiba) ICD2011-2 |
In this paper, first, the technical trend for high-bandwidth NAND flash memories is introduced. Second, an embedded DRAM... [more] | ICD2011-2 pp.7-12 |
| ICD | 2010-04-22 14:20 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
Overview of Chain FeRAM Technology and Scalable Shield-Bitline-Overdrive Technique Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima (Toshiba) ICD2010-8 |
This paper presents an overview of chain FeRAM technology, and a new scalable shield-bitline-overdrive technique. First,... [more] | ICD2010-8 pp.41-46 |
| ICD | 2009-04-13 12:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Invited Talk]
A 1.6GB/s DDR2 128Mb Chain FeRAM with Scalable Octal Bitline and Sensing Schemes Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko Dohmae (Toshiba Corp.) ICD2009-1 |
Ferroelectric RAMs (FeRAMs) are expected to be the next generation semiconductor memory for their fast access speed (com... [more] | ICD2009-1 pp.1-6 |
| SDM | 2007-03-15 15:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Key Process Technology of Reliable Sub Micron Capacitor for High Density Chain-FeRAM Koji Yamakawa, Tohru Ozaki, Hiroyuki Kanaya, Iwao Kunishima, Yoshinori Kumura, Yoshiro Shimojo, Susumu Shuto, Osamu Hidaka, Yuki Yamada, Soi chi Yamazaki, Takeshi Hamamoto, Shinichiro Shiratake, Daisaburo Takashima, Tadashi Miyakawa, Sumito Ohtsuki (Toshiba) |
[more] | SDM2006-259 pp.27-32 |
| ICD | 2006-04-13 13:00 |
Oita | Oita University | [Special Invited Talk]
Techniques and Scaling Scenario for Chain FeRAM Daisaburo Takashima (Toshiba) |
A chain FeRAM architecture is the best solution to realize high-density, high-speed and low power nonvolatile memory. In... [more] | ICD2006-6 pp.31-36 |
| ICD | 2006-04-13 16:40 |
Oita | Oita University | [Panel Discussion]
What is your urgent task in R/D of new embedded memories? Hideto Hidaka (Renesas), Masao Taguchi (SPANSION), Takayuki Kawahara (Hitachi), Daisaburo Takashima (Toshiba), Shuichi Ueno (Renesas), Masashi Takata (Kanazawa Univ.), Masafumi Takahashi (Toshiba) |
Recent advent of emerging memory devices circa 2000 has seen discussions directed mainly to stand-alone memory applicati... [more] | ICD2006-9 p.49 |
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