IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2020-01-28
14:45
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Can in-memory/Analog Accelerators be a Silver Bullet for Energy-efficient Inference?
Jun Deguchi, Daisuke Miyashita, Asuka Maki, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Ryuichi Fujimoto (KIOXIA) SDM2019-85
This presentation introduces and discuss recent trends on in-memory/analog computing for deep learning inference, which ... [more] SDM2019-85
p.11
ICD 2014-04-18
11:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
Keiichi Kushida, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Azuma Suzuki, Yusuke Niki, Miyako Shizuno, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2014-13
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] ICD2014-13
pp.65-70
ICD 2013-04-12
13:30
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Talk] A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe (Toshiba) ICD2013-18
A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monit... [more] ICD2013-18
pp.91-96
ICD 2013-04-12
14:20
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO
Miyako Shizuno, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2013-19
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] ICD2013-19
pp.97-102
ICD 2011-04-19
09:55
Hyogo Kobe University Takigawa Memorial Hall A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static ... [more] ICD2011-9
pp.49-54
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan