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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
IE, ITS, ITE-AIT, ITE-HI, ITE-ME, ITE-MMS, ITE-CE [detail] 2017-02-20
10:00
Hokkaido Hokkaido Univ. Inter Prediction method based on efficient memory bandwidth for HEVC real-time encoding
Kodai Miyajima, Gen Fujita (Osaka Electro-Communication Univ.) ITS2016-42 IE2016-100
 [more] ITS2016-42 IE2016-100
pp.1-6
IE, ITS, ITE-AIT, ITE-HI, ITE-ME, ITE-MMS, ITE-CE [detail] 2017-02-21
11:45
Hokkaido Hokkaido Univ. Fast Intra/Inter CU size Decision for H.265/HEVC using Machine Learning
Fengyu Tsai, Kei Furuta, Gen Fujita (Osaka Electro-Communication Univ.) ITS2016-51 IE2016-109
There is a heavy time complexity on HEVC(High Efficiency Video Coding) encoder, and the computation of CU(Coding Unit) s... [more] ITS2016-51 IE2016-109
pp.241-245
VLD 2014-03-04
10:45
Okinawa Okinawa Seinen Kaikan An Approach of Rate-Distortion Optimized Quantization and its Evaluation
Genki Moriguchi, Hajime Sawano, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.) VLD2013-145
Rate-distortion optimized quantization (RDOQ) is becoming a popular technology to improve its video coding performance.
... [more]
VLD2013-145
pp.67-72
VLD 2014-03-04
11:10
Okinawa Okinawa Seinen Kaikan An Hardware Implementation of Motion Estimation Technology Using High Level Synthesis
Shota Nagai, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.) VLD2013-146
Recently, video coding technology is used widely and is demanded higher quality and speeder. Therefore, we design hardwa... [more] VLD2013-146
pp.73-77
SIS, IPSJ-AVM 2012-09-20
11:05
Osaka Tottori Pref. Osaka Office An architecture of 4-mode-parallel 16x16 luma intra prediction for H.264/AVC encoder
Kenji Watanabe, Masanao Ise (Synthesis Corp.), Gen Fujita (Osaka Electro-Communication Univ.) SIS2012-19
 [more] SIS2012-19
pp.17-21
ICD, IE, SIP, IPSJ-SLDM [detail] 2011-10-24
16:20
Miyagi Ichinobo(Sendai) High efficiency VLSI architecture for H.264 CABAC decoder by using residual data accelalator
Gen Fujita (Osaka Electro-comm. Univ.), Kenji Watanabe (Synthesis Corp.), Toru Homemoto, Ryoji Hashimoto (Osaka Univ.) SIP2011-67 ICD2011-70 IE2011-66
 [more] SIP2011-67 ICD2011-70 IE2011-66
pp.31-35
SIS, SIP, IPSJ-AVM 2008-09-26
10:50
Fukuoka Tobata Campus, Kyushu Institute of Technology RDO based sub-pixel motion estimation method for H.264
Kosuke Kojima (Osaka Electro-communication Univ.), Ryoji Hashimoto (Osaka University), Gen Fujita (Osaka Electro-communication Univ.) SIP2008-99 SIS2008-34
This paper describes a motion estimation method for H.264 based on RDO(Rate-Distortion Optimization). RDO have not been ... [more] SIP2008-99 SIS2008-34
pp.53-58
SIP, ICD, IE, IPSJ-SLDM
(Joint) [detail]
2007-10-25
16:40
Fukushima Aidu-Higasiyama-Onsen Kuturogijuku VLSI Architecture of Multi-Symbol CABAC Decoder for H.264/AVC High Profile
Kimiya Kato, Ryoji Hashimoto (Osaka Univ.), Gen Fujita (Osaka Electro-Comm. Univ.), Takao Onoye (Osaka Univ.) SIP2007-121 ICD2007-110 IE2007-80
In H.264/AVC real-time decoding process, CABAC (Context-based Adaptive Binary Arithmetic Coding)
is an efficient entro... [more]
SIP2007-121 ICD2007-110 IE2007-80
pp.65-70
SIP, CAS, VLD 2006-06-23
10:15
Hokkaido Kitami Institute of Technology Efficient VLSI architecture for H.264 CABAC
Gen Fujita (Osaka Elector-Communication Univ.), Keita Okubo, Kenichi Jyoko, Makoto Saitsuji (Kinki Univ.), Takao Onoye (Osaka Univ.)
 [more] CAS2006-11 VLD2006-24 SIP2006-34
pp.19-23
CAS, SIP, CS 2006-03-06
12:00
Okinawa Univ of Ryukyu Improvement of Power Consumption and Response Time in Wireless Home Network
Kenji Watanabe (Osaka Univ.), Masanao Ise (Synthesis Corp.), Gen Fujita, Masahide Hatanaka, Takao Onoye (Osaka Univ.), Hiroaki Niwamoto, Ikuo Keshi (Sharp Corp.), Isao Shirakawa (Univ. of Hyogo)
In this paper, improvement of power consumption and response time is proposed dedicatedly for wireless home network. Ex... [more] CAS2005-100 SIP2005-146 CS2005-93
pp.25-30
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