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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM, ED (Workshop) |
2012-06-27 14:00 |
Okinawa |
Okinawa Seinen-kaikan |
A chip scale wafer level packaging for LED using surface aligning technique. Jin Kwan Kim, Hee Chul Lee (KAIST) |
A silicon based wafer level packaging (WLP) for LED, which can be adopted for chip scale package and batch process witho... [more] |
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SDM, ED |
2009-06-24 17:45 |
Overseas |
Haeundae Grand Hotel, Busan, Korea |
A Study on Lateral Surface Treatment of the CdTe X-ray image-sensor Jin Kwan Kim (KAIST), Keedong Yang (i3system Conp.), Yong Soo Lee (KAIST), Hee Chul Lee (KAIST/National Nanofab Center) ED2009-69 SDM2009-64 |
[more] |
ED2009-69 SDM2009-64 pp.83-86 |
SDM, ED |
2008-07-10 10:40 |
Hokkaido |
Kaderu2・7 |
A Study on Poly(3,4-ethylenedioxythiophene):Poly(styrene sulfonate) (PEDOT:PSS) Films for The Microbolometer Applications Hyeok Jun Son, Il Woong Kwon (KAIST), Ho Jun You (ETRI), Yong Soo Lee, Hee Chul Lee (KAIST) ED2008-68 SDM2008-87 |
We present Poly(3,4-ethylenedioxythiophene):Poly(Styrene sulfonate)(PEDOT:PSS) films for application in a bolometer, a k... [more] |
ED2008-68 SDM2008-87 pp.149-154 |
SDM, ED |
2008-07-11 13:50 |
Hokkaido |
Kaderu2・7 |
Study on Gate Around Transistor (GAT) Layout for Radiation Hardness Min-su Lee, Young-Soo Lee, Chul-Bum Kim, Young-Ho Kim (KAIST), Byoung-Gon Yu, Hee Chul Lee (ETRI) ED2008-91 SDM2008-110 |
We designed a Gate Around Transistor (GAT) layout for radiation hardness. A GAT MOSFET layout with an improved guard rin... [more] |
ED2008-91 SDM2008-110 pp.275-280 |
SDM, ED |
2008-07-11 14:05 |
Hokkaido |
Kaderu2・7 |
Low Power Pixel-Level ADC for a Micro-Bolometer Dong-Heon Ha, Chi Ho Hwang (KAIST), Woo Seok Yang (ETRI), Yong Soo Lee, Hee Chul Lee (KAIST) ED2008-92 SDM2008-111 |
[more] |
ED2008-92 SDM2008-111 pp.281-284 |
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