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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2015-01-27
11:40		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Coupled Monte Carlo Simulation of Transient Electron-Phonon Transport in Small FETs
Yoshinari Kamakura, Indra Nur Adisusilo, Kentaro Kukita, Go Wakimura (Osaka Univ.), Shunsuke Koba, Hideaki Tsuchiya (Kobe Univ.), Nobuya Mori (Osaka Univ.) SDM2014-139		  [more] SDM2014-139
pp.17-20
SDM 2014-11-07
11:15		 Tokyo Kikai-Shinko-Kaikan Bldg. Quasi-Ballistic Transport Parameters in Si Double-Gate MOSFETs Extracted Using Monte Carlo Method
Hideaki Tsuchiya, Ryoma Ishida (Kobe Univ.), Yoshinari Kamakura, Nobuya Mori (Osaka Univ.), Shigeyasu Uno (Ritsumeikan Univ.), Matsuto Ogawa (Kobe Univ.) SDM2014-105		 Recently, we have developed a Monte Carlo simulator for accurately extracting quasi-ballistic transport parameters in MO... [more] SDM2014-105
pp.53-58
SDM 2013-11-15
13:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Quantum transport simulation of ultrasmall III-V MOSFETs using Wigner Monte Carlo approach
Masaki Ohmori, Shunsuke Koba, Yosuke Maegawa (Kobe Univ.), Hideaki Tsuchiya (Kobe Univ./JST), Yoshinari Kamakura, Nobuya Mori (Osaka Univ./JST), Matsuto Ogawa (Kobe Univ.) SDM2013-111		 In this study, the impact of source-drain (SD) direct tunneling in III-V metal-oxide-semiconductor field-effect transist... [more] SDM2013-111
pp.65-70
SDM 2011-11-11
10:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Comparisons of Ballistic Device Performances of Si Nanowire and InAs Nanowire FETs based on First-Principles Band Structure Calculation
Naoya Takiguchi, Shunsuke Koba, Hideaki Tsuchiya, Matsuto Ogawa (Kobe Univ.) SDM2011-121		 In this paper, we study the band structures of <110>-oriented Si and InAs nanowires based on a first-principles calculat... [more] SDM2011-121
pp.33-38
SDM 2010-02-05
13:30		 Tokyo Kikai-Shinko-Kaikan Bldg. Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9)
M. Iguchi, S. Yokogawa, Hirokazu Aizawa, Y. Kakuhara, Hideaki Tsuchiya, Norio Okada, Kiyotaka Imai, M. Tohara, K. Fujii (NEC Electronics), T. Watanabe (Toshiba) SDM2009-186		 Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.... [more] SDM2009-186
pp.25-29
SDM [detail] 2008-11-14
16:15		 Tokyo Kikai-Shinko-Kaikan Bldg. Three-Dimensional Quantum Transport Simulation of Si-Nanowire Transistors
Yoshihiro Yamada, Hideaki Tsuchiya, Matsuto Ogawa (Kobe Univ.) SDM2008-182		 Si-nanowire transistors (SNWTs) are promising candidates as extremely downscaled MOSFETs for the future Si-VLSIs. To und... [more] SDM2008-182
pp.77-82
SDM [detail] 2008-11-14
16:40		 Tokyo Kikai-Shinko-Kaikan Bldg. First-Principles Simulation of Electronic Bandstructures on Nanoscaled-Si Channels with Strain Effects
Tadashi Maegawa, Tsuneki Yamauchi, Takeshi Hara, Hideaki Tsuchiya, Matsuto Ogawa (Kobe Univ.) SDM2008-183		 In this paper, we present a comparative computational study on strain effects in Si nanostructures including bulk, thin ... [more] SDM2008-183
pp.83-88
SDM, VLD 2007-10-30
10:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Comparative Study on Drive Current of non-Si n-Channel MOSFETs based on Quantum-Corrected Monte Calro Simulation
Takashi Mori, Yuusuke Azuma, Hideaki Tsuchiya (Kobe Univ.) VLD2007-51 SDM2007-195		 A variety of new channel materials have been intensively studied to achieve a continuous enhancement in drive current of... [more] VLD2007-51 SDM2007-195
pp.5-10
SDM, VLD 2006-09-26
15:00		 Tokyo Kikai-Shinko-Kaikan Bldg. To be announced
Hideaki Tsuchiya, Kazuya Fujii, Takashi Mori, Tanroku Miyoshi (Kobe Univ.) 		Quasi-ballistic transport is one of the technology boosters for drive current enhancement of Si-MOSFETs. In this paper, ... [more] VLD2006-47 SDM2006-168
pp.49-54
 Results 1 - 9 of 9  /   
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