IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 338  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-29
11:25
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
A Message Passing Interface Library for High-Level Synthesis on M-KUBOS Multi-FPGA systems
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.)
 [more]
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
09:55
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops
Daiki Yokoyama, Kimiyoshi Usami (SIT), Aika Kamei, Hideharu Amano (Keio Univ.)
 [more]
RECONF 2022-09-07
14:35
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
Simulation for a CNN implementation on a multi-FPGA system with system-C description
Shao Ningyu, Hiroaki Suzuki (Keio Univ.), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ.), Hideharu Amano (Keio Univ.) RECONF2022-27
 [more] RECONF2022-27
pp.7-12
RECONF 2022-09-07
15:20
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
RECONF2022-28 (To be available after the conference date) [more] RECONF2022-28
pp.13-14
RECONF 2022-09-07
15:30
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
RECONF2022-29 (To be available after the conference date) [more] RECONF2022-29
pp.15-16
RECONF 2022-09-07
15:40
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
RECONF2022-30 (To be available after the conference date) [more] RECONF2022-30
pp.17-18
RECONF 2022-09-07
15:50
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
RECONF2022-31 (To be available after the conference date) [more] RECONF2022-31
pp.19-20
RECONF 2022-09-07
16:00
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
[Short Paper]
Zuquan Qin, Weu Kaijie, Hideharu Amano (Keio Univ.), Kazuhiro Nakadai (TIT) RECONF2022-32
(To be available after the conference date) [more] RECONF2022-32
pp.21-22
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
13:30
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Masahiro Iida (Kumamoto Univ.), Hideharu Amano (Keio Univ.) CPSY2022-8 DC2022-8
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] CPSY2022-8 DC2022-8
pp.41-46
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
14:00
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)

Takumi Inage, Kensuke Iizuka, Hideharu Amano (Keio Univ.) CPSY2022-9 DC2022-9
(To be available after the conference date) [more] CPSY2022-9 DC2022-9
pp.47-52
CPSY, DC, IPSJ-ARC [detail] 2022-07-29
09:45
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
CPSY2022-13 DC2022-13 (To be available after the conference date) [more] CPSY2022-13 DC2022-13
pp.71-76
RECONF 2022-06-08
11:35
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Introduction of Power Monitoring Tool for FPGA Clusters and Power Analysis of FPGA Clusters
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ) RECONF2022-18
Low power consumption is a significant advantage of FPGA clusters.
This study reports the detailed power consumption an... [more]
RECONF2022-18
pp.80-85
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
13:50
Online Online Implementation of an Application Mapping Tool for a Circuit-Switched Multi-FPGA System
Kohei Ito (Keio Univ.), Ryota Yasudo (Kyoto Univ.), Hideharu Amano (Keio Univ.) CPSY2021-48 DC2021-82
(To be available after the conference date) [more] CPSY2021-48 DC2021-82
pp.20-25
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
14:30
Online Online Compression of configuration data in Scalable Logic Module
Souhei Takagi, Naoya Niwa, Yoshiya Shikama, Yosuke Yanai, Hideharu Amano (Keio Univ), Yuya Nakasato, Daiki Amagasaki, Masahiro Iida (Kumamoto Univ) CPSY2021-49 DC2021-83
(To be available after the conference date) [more] CPSY2021-49 DC2021-83
pp.26-31
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-11
14:50
Online Online A Study on an Acceleration of Graph-Based SLAM with FPGA
Hajime Takishita, Yuan He, Masaaki Kondo, Hideharu Amano (Keio Univ.n) CPSY2021-62 DC2021-96
(To be available after the conference date) [more] CPSY2021-62 DC2021-96
pp.103-108
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
10:45
Online Online An Implementation of a Real-time Stereo Matching System on FPGA
Kaijie Wei (Keio Univ.), Yuki Kuno (Marelli Corp.), Masatoshi Arai (Saitama Univ.), Hideharu Amano (Keio Univ.) VLD2021-65 CPSY2021-34 RECONF2021-73
To make full use of stereo data in autonomous driving system, the techniques to generate depth-map in real-time are nece... [more] VLD2021-65 CPSY2021-34 RECONF2021-73
pp.90-95
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
11:50
Online Online VLD2021-67 CPSY2021-36 RECONF2021-75 (To be available after the conference date) [more] VLD2021-67 CPSY2021-36 RECONF2021-75
pp.102-107
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
17:05
Online Online Hard-to-Detect Hardware Trojan Attack Exploiting Coherence Control Mechanisms
Yoshiya Shikama (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2021-75 CPSY2021-44 RECONF2021-83
(To be available after the conference date) [more] VLD2021-75 CPSY2021-44 RECONF2021-83
pp.148-153
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-01
10:35
Online Online Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28
pp.19-24
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-02
09:20
Online Online The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44
We are currently developing a multi-FPGA system, Flow-in-Cloud (FiC) system. FiC directly interconnects multiple middle-... [more] VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44
pp.111-116
 Results 1 - 20 of 338  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan