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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EMCJ | 2023-06-09 14:25 |
Hokkaido | Otaru Chamber of Commerce & Industry (Primary: On-site, Secondary: Online) |
Evaluation and Countermeasure for Electromagnetic Interference with Mobile Communication Systems inside Industrial Drones Ryota Sakai (Kobe Univ.), Koh Watanabe (NICT), Sosuke Ashida, Hiraku Uehara, Satoshi Tanaka, Makoto Nagata (Kobe Univ.), Hideki Osaka (toriR Lab.), Atsushi Nakamura (UTI)  EMCJ2023-23 |
[more] | EMCJ2023-23 pp.58-61 |
| NLP | 2015-04-24 13:55 |
Kagawa | Kagawa Social Welfare Center | High Sensitive Detecting Technique for Weak Signal by Stochastic Resonance Wen Li, Hisaaki Kanai, Kengo Imagawa, Masami Makuuchi, Hideki Osaka (Hitachi) NLP2015-21 |
Stochastic resonance (SR), a phenomenon that signals can be enhanced with especial noise strength in a non-linear system... [more] | NLP2015-21 pp.99-104 |
| EMCJ | 2013-11-22 13:30 |
Tokyo | Tokyo Denki Univ. | Estimation of Conducted Emission from Automotive Components by Using Noise Equivalent Circuit Makoto Torigoe, Yoshiyuki Tsuchie, Yasuo Yahagi, Takashi Suga, Hideki Osaka (Hitachi), Takayuki Inagaki (Hitachi Automotive) EMCJ2013-92 |
Reduction of switching noise emitted from automotive components is required, because of increasing noise due to the high... [more] | EMCJ2013-92 pp.7-10 |
| EMCJ, ITE-BCT | 2013-03-08 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Modeling and Noise Propagation Mechanism of Electrostatic Discharge on PCB in Contact Mode Yasumaro Komiya, Hitoshi Yokota, Tsutomu Hara, Hideki Osaka, Takashi Suga (Hitachi) EMCJ2012-124 |
The accuracy of electromagnetic field simulations of the electrostatic discharge test into a PCB in contact mode has bee... [more] | EMCJ2012-124 pp.7-12 |
| EMCJ, ITE-BCT | 2013-03-08 10:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | ESD Noise Propagation Mechanism of the Transmission Line in the Same Side as the Injection Point on PCB Tsutomu Hara, Yasumaro Komiya, Takashi Suga, Hideki Osaka, Hitoshi Yokota (Hitachi) EMCJ2012-125 |
The behavior of ESD noise was analyzed by experiments and numerical simulation. ESD was directly applied to the GND trac... [more] | EMCJ2012-125 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Invited Talk]
High-Speed Interconnect Technologies Yutaka Uematsu, Go Shinkai, Satoshi Muraoka, Masayoshi Yagyu, Hideki Osaka (Hitachi) CPM2012-112 ICD2012-76 |
[more] | CPM2012-112 ICD2012-76 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | High Sensitive Detection of Low S/N ratio Signal by Bistable Potential Circuit Hisaaki Kanai, Wen Li, Kengo Imagawa, Masami Makuuchi, Yutaka Uematsu, Hideki Osaka (Hitachi, Ltd.) VLD2012-93 DC2012-59 |
Stochastic resonance (SR), a phenomenon that signals can be enhanced with especial noise strength in a non-linear system... [more] | VLD2012-93 DC2012-59 pp.195-200 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 16:00 |
Kochi | Kochi City Culture-Plaza | [Panel Discussion]
EMC Circuit Design and Jisso Design for System LSI
-- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side -- Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) CPM2009-142 ICD2009-71 |
Nowadays, a JISSO design is very important to get the target performance out of a system LSI. More specifically, co-desi... [more] | CPM2009-142 ICD2009-71 pp.47-49 |
| EMCJ | 2009-11-20 13:55 |
Tokyo | Aoyama Gakuin Univ. (Aoyama Campus) | Measurement Techniques for On-chip Power Supply Noise Waveforms based on Delay Observation in Inverter Chain Circuits Yutaka Uematsu, Hideki Osaka, Eiichi Suzuki, Masayoshi Yagyu, Tatsuya Saito (Hitachi Co Ltd.) EMCJ2009-83 |
To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measu... [more] |
EMCJ2009-83 pp.25-30 |
| EMCJ | 2009-11-20 14:20 |
Tokyo | Aoyama Gakuin Univ. (Aoyama Campus) | PDN Analysis of LSI Package in Short TAT using TMM and Approximated Equivalent Circuit Masahiro Toyama, Yutaka Uematsu, Hideki Osaka (Hitachi,LTD.), Motoo Suwa, Atsushi Nakamura (Renesas Tech Corp.) EMCJ2009-84 |
For the efficient optimizing of LSI package PDN (Power Distribution Network) in early stage of the design, short TAT ana... [more] | EMCJ2009-84 pp.31-36 |
| CPM, ICD | 2008-01-18 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board that Simulates Memory Module Yutaka Uematsu, Hideki Osaka (Hitachi), Yoji Nishio, Susumu Hatano (Elpida) CPM2007-139 ICD2007-150 |
Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting ade... [more] | CPM2007-139 ICD2007-150 pp.65-69 |
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