IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM, ITE-IST [detail] 2016-08-02
10:40
Osaka Central Electric Club [Invited Talk] Patch-type EEG System with Stretchable Electrode Sheet for Medical Application
Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Toshikazu Nezu, Masaya Kondo (Osaka Univ.), Kenichi Sasai (Panasonic), Masayuki Iwase, Hideki Satake, Akio Yoshida (Mektron), Mitsuru Kikuchi (Kanazawa Univ.), Tsuyoshi Sekitani (Osaka Univ.) SDM2016-56 ICD2016-24
 [more] SDM2016-56 ICD2016-24
p.63
SDM 2006-06-22
11:20
Hiroshima Faculty Club, Hiroshima Univ. Influence of Nitrogen and Hydrogen on NBTI in Ultrathin SiON
Yuichiro Mitani, Hideki Satake (Toshiba Corp.)
NBTI(Negative Bias Temperature Instability) has become increasingly serious in the context of effort to develop highly r... [more] SDM2006-57
pp.87-92
SDM 2006-06-22
14:15
Hiroshima Faculty Club, Hiroshima Univ. unknown
Wataru Mizubayashi (MIRAI-ASRC, AIST), Arito Ogawa, Toshihide Nabatame, Hideki Satake (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, Univ. of Tokyo)
 [more] SDM2006-61
pp.107-111
ICD, SDM 2005-08-19
11:10
Hokkaido HAKODATE KOKUSAI HOTEL Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo)
Threshold voltage (Vth) tuning by engineering Fermi-level pinning (FLP) on HfAlOx(N) dielectrics is demonstrated for CMO... [more] SDM2005-148 ICD2005-87
pp.31-36
 Results 1 - 4 of 4  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan