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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2018-04-20
Tokyo   [Invited Lecture] An Implementation of 2RW Dual-Port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT
Yohei Sawada, Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Makoto Yabuuchi (REL), Yoshihiro Shinozaki, Kyoji Ito (NSW), Shinji Tanaka, Nii Koji, Shiro Kamohara (REL) ICD2018-8
 [more] ICD2018-8
SDM, ICD, ITE-IST [detail] 2017-07-31
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. A 65 nm 1.0V 1.84ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT
Makoto Yabuuchi, Koji Nii, Shinji Tanaka (Renesas), Shinozaki Yoshihiro (Nippon Systemware), Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Shiro Kamohara (Renesas) SDM2017-33 ICD2017-21
 [more] SDM2017-33 ICD2017-21
SDM 2016-10-26
Miyagi Niche, Tohoku Univ. [Invited Talk] Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation
Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] SDM2016-71
SDM, ICD 2015-08-24
Kumamoto Kumamoto City Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via
Hiroki Shinkawata, Nobuo Tsuboi (REL), Atsushi Tsuda (RSD), Shingo Sato (Kansai), Yasuo Yamaguchi (REL) SDM2015-58 ICD2015-27
We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting ar... [more] SDM2015-58 ICD2015-27
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