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All Technical Committee Conferences (All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2022-06-07 14:50 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Vector Register Sharing Mechanism for Hardware Acceleration Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT)  RECONF2022-5 |
In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] | RECONF2022-5 pp.26-31 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:50 |
Online | Online | Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] | VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 15:35 |
Online | Online | Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT) VLD2021-72 CPSY2021-41 RECONF2021-80 |
In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasing... [more] | VLD2021-72 CPSY2021-41 RECONF2021-80 pp.132-137 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 13:10 |
Online | Online | Automated architecture exploration on Scala-based hardware development environment Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) VLD2020-62 CPSY2020-45 RECONF2020-81 |
In recent years, reconfigurable architectures such as FPGAs have been attracting more and more attention. Design Space... [more] |
VLD2020-62 CPSY2020-45 RECONF2020-81 pp.131-136 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Domain Knowledge-aware Machine Learning System with Rule-based Guiding Tomoaki Shikina, Daichi Teruya, Hironori Nakajo (TAT) CPSY2019-44 |
Data-driven methods in machine learning rely only on the statistical nature of the data. Therefore, its predictions coul... [more] | CPSY2019-44 pp.23-28 |
| RECONF | 2019-05-09 15:20 |
Tokyo | Tokyo Tech Front | High Level Synthesis of Recursive Description in a CPU+FPGA Co-design framework based on Ruby Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) RECONF2019-6 |
(To be available after the conference date) [more] | RECONF2019-6 pp.29-34 |
| RECONF | 2018-05-24 15:20 |
Tokyo | GATE CITY OHSAKI | A design of autoscale mechanism using high level synthesis tool for autonomous distributed system Daichi Teruya, Hironori Nakajo (TUAT) RECONF2018-9 |
Since cloud computing has become widespread for various purposes, it is drawing attention to use FPGAs. When utilizing ... [more] |
RECONF2018-9 pp.45-50 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2018-03-08 15:25 |
Shimane | Okinoshima Bunka-Kaikan Bldg. | Selecting a Rule Set of the Logical Inference System with Machine Learning Shozo Takeoka, Tomoaki Shikina, Hironori Nakajo (TUAT) CPSY2017-142 DC2017-98 |
Since modern logical inference system needs a huge rule-base which is increasing more and more, search space can be red... [more] | CPSY2017-142 DC2017-98 pp.197-202 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 09:15 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT) VLD2017-76 CPSY2017-120 RECONF2017-64 |
[more] | VLD2017-76 CPSY2017-120 RECONF2017-64 pp.83-88 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2017-77 CPSY2017-121 RECONF2017-65 |
We expect reduce CPU resource consumptions by offloading processing stream data, which are incessantly generated such a... [more] |
VLD2017-77 CPSY2017-121 RECONF2017-65 pp.89-94 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 15:15 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs Yoshio Murata, Hironori Nakajo (TUAT) VLD2017-86 CPSY2017-130 RECONF2017-74 |
[more] | VLD2017-86 CPSY2017-130 RECONF2017-74 pp.151-156 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | IoT Platform using an MCU-FPGA Hybrid System and Feasibility Study of Wireless Configuration Ryota Suzuki, Hironori Nakajo (TUAT) RECONF2017-45 |
An MCU (Micro Control Unit) which is used in an embedded system has been recently equipped with a communication function... [more] | RECONF2017-45 pp.49-54 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 09:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2016-80 CPSY2016-116 RECONF2016-61 |
[more] | VLD2016-80 CPSY2016-116 RECONF2016-61 pp.61-66 |
| RECONF | 2016-05-19 14:15 |
Kanagawa | FUJITSU LAB. | Efficiency Execution of Split Circuit in a Scalable Hardware System by Signal Compression Yoshio Murata, Hironari Yoshiuchi, Hironori Nakajo (TUAT) RECONF2016-8 |
(To be available after the conference date) [more] | RECONF2016-8 pp.35-40 |
| RECONF | 2016-05-20 10:45 |
Kanagawa | FUJITSU LAB. | A Sound Field Visualizer with Java-based High Level Synthesis Tool and CoRAM Architecture Synthesis Framework Daichi Teruya, Daichi Miyazaki, Hironori Nakajo (TUAT) RECONF2016-20 |
Currently the number of devices which uses multiple sensors has been increasing due to recent significant interest on th... [more] | RECONF2016-20 pp.97-102 |
| RECONF | 2015-09-18 14:55 |
Ehime | Ehime University | Overview of the Reconfigurable Virtual Accelerator ReVA Hironori Nakajo, Yuki Oigo (TUAT), Shozo Takeoka (AXE), Masashi Takemoto (BeatCraft), Takefumi Miyoshi (Wasalabo) RECONF2015-40 |
[more] | RECONF2015-40 pp.45-50 |
| PRMU, CNR | 2015-02-20 16:30 |
Miyagi | Smart space for unconstrained monitoring of office activity
-- Automatic estimation of communication and task activities -- Kinya Fujita, Masano Nakayama, Hiroaki Murata, Hitomi Yokoyama, Seiji Hotta, Ikuko Shimizu, Takafumi Saito, Toshiyuki Kondo, Hironori Nakajo, Kaori Fujinami, Katsuhide Fujita (TUAT) PRMU2014-155 CNR2014-70 |
For long-term automatic analysis of office activities, an intelligent environment is desired, which enables unconstraine... [more] | PRMU2014-155 CNR2014-70 pp.215-220 |
|
| CPSY, DC (Joint) |
2014-07-29 09:00 |
Niigata | Toki Messe, Niigata | Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17 |
In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HD... [more] | CPSY2014-17 pp.43-48 |
| RECONF | 2014-06-12 15:35 |
Miyagi | Katahira Sakura Hall | Implementation of a RISC Processor with a Complex Instruction Accelerator
-- Return to a CISC -- Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) RECONF2014-13 |
In this paper, we propose a RISC processor with an accelerator which can execute a complex instruction with a co-proces... [more] |
RECONF2014-13 pp.67-72 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | A Storing and Regenerating Signal Information in a Scalable Hardware System Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60 |
In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating ... [more] | VLD2013-106 CPSY2013-77 RECONF2013-60 pp.25-30 |
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