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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS [detail] | 2022-03-08 09:55 |
Online | Online | Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology)  VLD2021-92 HWS2021-69 |
Statistical methods for predicting the performance of large-scale integrated circuits (LSIs) manufactured on a wafer are... [more] | VLD2021-92 HWS2021-69 pp.87-92 |
| HWS, VLD | 2019-02-28 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan | A SPICE Model Parameter Extraction Environment Using Automatic Differentiation Aoi Ueda (NNCT), Michihiro Shintani (NAIST), Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT), Michiko Inoue (NAIST) VLD2018-117 HWS2018-80 |
Accuracy of circuit simulation highly relys on two techniques: compact modeling and parameter extraction. As increasing ... [more] | VLD2018-117 HWS2018-80 pp.145-150 |
| DC | 2014-02-10 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Module Coupling Overhead Aware Scan Chain Construction Meguru Komatsu, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-79 |
It is necessary to minimize the impact on the layout of the design changes to Design for Testability (DFT). Especially,... [more] |
DC2013-79 pp.1-5 |
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| DC | 2014-02-10 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Suitable Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path Ryo Ogawa, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-82 |
The power consumption of Very Large Scale Integrated circuit (VLSI) testing is a significant problem. The VLSI should be... [more] | DC2013-82 pp.19-24 |
| DC | 2014-02-10 12:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Efficient Test Pattern Generator based on Mersenne Twister algorithm Sayaka Satonaka, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-86 |
To perform a high reliable manufacturing test with a reasonable cost, LFSR is widely used as test pattern generator. How... [more] | DC2013-86 pp.43-48 |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| IN, NS (Joint) |
2009-03-03 11:10 |
Okinawa | Okinawa-Zanpamisaki Royal Hotel | Analysis on characteristics of ZigBee propagation by people and its application to crowd density estimation system Masayuki Nakatsuka, Hiroshi Iwatani, Jiro Katto (Waseda Univ.) NS2008-173 |
Recently, it is an important topic to estimate the number of people in various places for an automatic monitoring system... [more] | NS2008-173 pp.171-176 |
| SIS, SIP, IPSJ-AVM | 2008-09-25 15:25 |
Fukuoka | Tobata Campus, Kyushu Institute of Technology | Resource Oriented Architecture for Visual Sensor Networks Hiroshi Iwatani, Masayuki Nakatsuka, Yutaro Takayanagi, Jiro Katto (Waseda Univ.) |
Sensor Network has been a hot research topic for the past decade and has moved its’ phase into using multimedia sensors ... [more] | SIP2008-93 SIS2008-28 pp.21-26 |
| VLD, CAS, SIP | 2008-06-27 09:40 |
Hokkaido | Hokkaido Univ. | An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST) CAS2008-21 VLD2008-34 SIP2008-55 |
Information on false paths in a circuit is useful for design and test. The use of this information may contribute not o... [more] | CAS2008-21 VLD2008-34 SIP2008-55 pp.13-18 |
| MVE, IE | 2007-07-09 16:30 |
Shizuoka | Resorpia Atami | Design of Environmental Information Web Services and Visualization Application Hiroshi Iwatani, Masayuki Nakatsuka, Jiro Katto (Waseda Univ.) IE2007-26 MVE2007-29 |
In this research we propose a system design of visualized applications, in which a user carries a mobile terminal enabli... [more] | IE2007-26 MVE2007-29 pp.37-42 |
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