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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 14:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Design and Evaluation of A Suboptimal Unidirectional Network Tomohiro Totoki, Hiroshi Nakahara, Daichi Fujiki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)  VLD2016-101 CPSY2016-137 RECONF2016-82 |
(To be available after the conference date) [more] | VLD2016-101 CPSY2016-137 RECONF2016-82 pp.215-220 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 09:55 |
Nagasaki | Fukue Bunka Hall/Rodou Fukushi Center | An Effective Virtual Channel Allocation Method for Deterministic Deadlock-free Routing Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2015-148 DC2015-102 |
Distributed routing methods with small routing tables are scalable design on irregular networks for large-scale High Per... [more] | CPSY2015-148 DC2015-102 pp.163-168 |
| ICD, CPSY | 2015-12-18 14:30 |
Kyoto | Kyoto Institute of Technology | A Low Latency Distributed Routing Method for Random Topologies in HPC Networks Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) ICD2015-90 CPSY2015-103 |
End-to-end network latency has become an important issue for parallel application on large-scale High Performance Comput... [more] | ICD2015-90 CPSY2015-103 pp.105-110 |
| ICD, CPSY | 2015-12-18 14:55 |
Kyoto | Kyoto Institute of Technology | Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint Hiroshi Nakahara, Daichi Fujiki, Seiichi Tade, Ryota Yasudo, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Koji Nakano (Hiroshima Univ.), Hideharu Amano (Keio Univ.) ICD2015-91 CPSY2015-104 |
(To be available after the conference date) [more] | ICD2015-91 CPSY2015-104 pp.111-116 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-06 17:30 |
Oita | B-Con Plaza (Beppu) | A Layout Method of High-Radix Topology onto 3D Stacking Chips Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2015-43 |
(To be available after the conference date) [more] | CPSY2015-43 pp.275-280 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Scalable and Low Latency Structure for Castle of Chips Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-79 |
Castle of Chips(CoC) is a chip stacking structure without chip-to-chip wired interconnection. Instead, each chip uses in... [more] | CPSY2014-79 pp.39-44 |
| CPM, EE | 2012-02-10 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Study of Lithium-ion Battery Degradation Model
-- Formulation by Negative Electrode Capacity and SEI Degradation -- Hiroshi Nakahara, Tomoshi Aoki, Takahito Hirata, Masahiro Fukui (Ritsumeikan Univ.) EE2011-54 CPM2011-170 |
Degradation of the battery capacity is studied to make more efficient use of lithium-ion batteries that demand is growin... [more] | EE2011-54 CPM2011-170 pp.13-16 |
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