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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 26  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS 2018-04-13
10:20		 Fukuoka   [Invited Talk] Security of Information Infrastructure -- From viewpoints of CIO and CISO --
Hiroto Yasuura (Kyushu Univ.) HWS2018-1		 As a CIO and a CISO of a national university, actual problems and issues concerning security in the information infrastr... [more] HWS2018-1
pp.1-4
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-28
11:20		 Miyazaki NewWelCity Miyazaki An Interrupt Service Handler in Hardware for Ultra-Low Latency Response
Naotaka Maruyama (Kernelon Silicon), Tohru Ishihara (Kyoto Univ.), Hiroaki Takada (Nagoya Univ.), Hiroto Yasuura (Kyushu Univ.) VLD2011-57 DC2011-33		 This paper proposes an interrupt processing in hardware for achieving ultra-low interrupt latency. Several types of mach... [more] VLD2011-57 DC2011-33
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-03
11:00		 Kochi Kochi City Culture-Plaza A Quantitative Evaluation of Security for Scan-based Side Channel Attack and Countermeasures
Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ) VLD2009-52 DC2009-39		 There is a potential that the secret information on an encryption LSI is leaked from a scan chain. There are many counte... [more] VLD2009-52 DC2009-39
pp.73-78
DC, CPSY 2009-04-21
13:50		 Tokyo Akihabara Satellite Campus, Tokyo Metropolitan Univ. Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units
Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) CPSY2009-5 DC2009-5		 This paper describes soft errors which are errors in LSI that are due to external radiation.The soft error rate (SER) wh... [more] CPSY2009-5 DC2009-5
pp.25-30
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2009-03-05
15:15		 Niigata Sado Island Integrated Development Center A Dynamic Management Technique of a Non-Uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-90 DC2008-81		 (To be available after the conference date) [more] CPSY2008-90 DC2008-81
pp.13-18
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2009-03-05
15:45		 Niigata Sado Island Integrated Development Center Single-Cycle-Accessible Two-Level Cache Architecture
Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82		 A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] CPSY2008-91 DC2008-82
pp.19-24
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-17
16:05		 Fukuoka Kitakyushu Science and Research Park Insertion-Point Selection of Canary FF for Timing Error Prediction
Yuji Kunitake (Kyushu Univ.), Toshinori Sato (Fukuoka Univ.), Seiichiro Yamaguchi, Hiroto Yasuura (Kyushu Univ.) 		The deep submicron semiconductor technologies increase parameter ariations. The increase in parameter variations require... [more] VLD2008-74 DC2008-42
pp.85-89
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-19
14:15		 Fukuoka Kitakyushu Science and Research Park [Invited Talk] A Business Model for BOP
Hiroto Yasuura (Kyushu Univ.) CPM2008-98 ICD2008-97		 Two thirds of people in the world are living in the severe situation without electricity and water supply. In the progre... [more] CPM2008-98 ICD2008-97
pp.51-53
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-19
15:30		 Fukuoka Kitakyushu Science and Research Park [Panel Discussion] Future Prospective of Semiconductor Devices in 2025 -- Based on Ishigaki Workshop by ICD --
Hiroto Yasuura (Kyushu Univ.), Osamu Karatsu (SRI International Japan), Haruhisa Ichikawa (Univ. of Electro-Communications), Wang, Shu Zhen (Univ. of Kitakyushu), Koji Kai (Panasonic), Minoru Fujishima (Univ. of Tokyo) CPM2008-100 ICD2008-99		 Exponential evolution represented by the Moore's law in an LSI brings rapid change and development of the social infrast... [more] CPM2008-100 ICD2008-99
p.61
ISEC, SITE, IPSJ-CSEC 2008-07-25
16:35		 Fukuoka Fukuoka Institute of System LSI Design Industry Illegal Copy Detection Framework for CAD Tools based on Watermarks Embedded in VHDL Codes
Kazuhide Fukushima, Shinsaku Kiyomoto, Toshiaki Tanaka (KDDI R&D Labs.), Kouichi Sakurai, Hiroto Yasuura (Kyushu Univ.) ISEC2008-58		  [more] ISEC2008-58
pp.169-176
ICD, IPSJ-ARC 2008-05-14
16:00		 Tokyo   Considering Performance and Area Overhead in DVS System Utilizing Input Variations
Yuji Kunitake (Kyushu U.), Toshinori Sato (Fukuoka U.), Hiroto Yasuura (Kyushu U.) 		The deep submicron semiconductor technologies increase parameter variations and thus the processor design becomes more d... [more] ICD2008-34
pp.93-98
VLD, IPSJ-SLDM 2008-05-09
11:40		 Hyogo Kobe Univ. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) VLD2008-9		 This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shr... [more] VLD2008-9
pp.13-18
DC 2008-02-08
14:15		 Tokyo Kikai-Shinko-Kaikan Bldg. An evaluation of encryption LSI testability against scan based attack
Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ.) DC2007-76		 Recently, an encryption LSI is embedded in a variety of digital products
for security and copyright protection. Most L... [more]		 DC2007-76
pp.57-62
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
10:05		 Fukuoka Kitakyushu International Conference Center A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) 		Memory systems consume a significant amount of the energy in embedded systems. Static code placement techniques using sc... [more] VLD2007-74 DC2007-29
pp.25-29
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
10:30		 Fukuoka Kitakyushu International Conference Center An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) 		This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories ... [more] VLD2007-75 DC2007-30
pp.31-36
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
15:35		 Fukuoka Kitakyushu International Conference Center An On-Chip Bus Architecture for Post-Fabrication Timing Calibration
Masaki Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) 		As the transistor size shrinks, the horizontal coupling capacitance between adjacent wires becomes dominant for wire loa... [more] VLD2007-79 DC2007-34
pp.55-60
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-21
13:00		 Fukuoka Kitakyushu International Conference Center [Fellow Memorial Lecture] Social Information Infrastructure and Dependable VLSI
Hiroto Yasuura (Kyushu Univ.) VLD2007-82 DC2007-37 RECONF2007-36		 Our daily lives heavily depends on the social information infrastructure, which includes a huge numbers of VLSI chips. V... [more] VLD2007-82 DC2007-37 RECONF2007-36
pp.1-6
SIP, ICD, IE, IPSJ-SLDM
(Joint) [detail]		 2007-10-26
15:10		 Fukushima Aidu-Higasiyama-Onsen Kuturogijuku -
Tadayuki Matsumura, Yuriko Ishitobi, Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ) 		 [more]
ICD, VLD 2007-03-07
17:20		 Okinawa Mielparque Okinawa A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits
Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) 		 [more] VLD2006-117 ICD2006-208
pp.67-72
ICD, VLD 2007-03-07
17:40		 Okinawa Mielparque Okinawa A Study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yuan Yang (Xi’an Univ. of Technology), Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) 		As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design f... [more] VLD2006-118 ICD2006-209
pp.73-78
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