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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 16:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)  VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 |
Recently, approximate computing has attracted attention as a method to reduce power and area for error-tolerant applicat... [more] | VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 pp.156-161 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 15:00 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On reduction of test patterns for a Multiplier Using Approximate Computing Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ) VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 |
In recent years, approximate computing has been used in error-tolerant applications. Several approximation methods have ... [more] | VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 pp.25-30 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:20 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 |
In this study, we have proposed a method to make the design-for-testability circuity function as a security mechanism by... [more] | VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 pp.156-161 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] | VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
| DC | 2022-03-01 13:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Delay Fault Test Pattern Generation of Fault Tolerant Design Using Approximate Computing Koji Makino, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2021-71 |
[more] | DC2021-71 pp.39-44 |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| DC | 2020-02-26 10:50 |
Tokyo | A study on temperature dependence on discrimination of resistive opens using machine learning-based anomaly detection Ryotaroh Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2019-88 |
[more] | DC2019-88 pp.13-18 |
|
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42 |
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs ... [more] |
VLD2018-56 DC2018-42 pp.119-124 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:50 |
Hiroshima | Satellite Campus Hiroshima | Study on the Applicability of ATPG Pattern for DFT Circuit Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44 |
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] | VLD2018-58 DC2018-44 pp.131-136 |
| DC | 2018-02-20 10:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79 |
TSV attracts attention as a new implementation method of interconnects between dies in 3DICs. However, faulty TSVs may ... [more] |
DC2017-79 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Design to Improve Open Defect Detection for Test Based on IDDT Appearance Time Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2017-49 DC2017-55 |
Increasing open defects has become a problem. We proposed a supply current test method with a built-in sensor for dete... [more] |
VLD2017-49 DC2017-55 pp.125-130 |
| DC | 2017-02-21 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79 |
Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] | DC2016-79 pp.29-34 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. ... [more] |
VLD2016-62 DC2016-56 pp.105-110 |
| DC | 2016-02-17 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-88 |
As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic v... [more] | DC2015-88 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 14:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-42 DC2015-38 |
The effect of a resistive open results in small delay in an IC. It is difficult to test small delay since signal delay a... [more] | VLD2015-42 DC2015-38 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | Investigation of the area reduction of observation part and control part in TSV fault detection circuit Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26 |
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] | VLD2014-72 DC2014-26 pp.3-8 |
| DC | 2014-02-10 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-80 |
In recent deep sub-micron (DSM) ICs, it is difficult to detect open and short defects since they do not behave like co... [more] |
DC2013-80 pp.7-12 |
| DC | 2014-02-10 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code Ryota Mori, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-88 |
BIST-aided scan test (BAST) has been proposed as one of the techniques that enhances scan-based BIST. The BAST architect... [more] | DC2013-88 pp.55-60 |
| DC | 2013-02-13 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84 |
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] | DC2012-84 pp.25-30 |
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