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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology [Poster Presentation]
Itaru Hida, Shinya Takamaeda, Masayuki Ikebe, Masato Motomura, Tetsuya Asai (Hokkaido Univ.) ICD2016-60 CPSY2016-66
In this paper, we propose a Bayesian branch prediction circuit consisting of an instruction-feature extractor and a naiv... [more] ICD2016-60 CPSY2016-66
p.39
ICD, CPSY 2014-12-01
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Poster Presentation] A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers
Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] ICD2014-82 CPSY2014-94
p.43
RECONF 2013-09-18
17:00
Ishikawa Japan Advanced Institute of Science and Technology A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-24
Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-e... [more] RECONF2013-24
pp.25-30
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