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Committee Date Time Place Paper Title / Authors Abstract Paper #
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-24
14:10		 Kochi Kochi University of Technology Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset
Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61		 This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61
pp.375-382
ISEC 2019-05-17
11:00		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology (from DSD 2018)
Jean-Luc Danger (Telecom ParisTech), Risa Yashiro (UEC), Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet (Telecom ParisTech), Kazuo Sakiyama (UEC), Noriyuki Miura, Makoto Nagata (Kobe University), Sylvain Guilley (Secure-IC) ISEC2019-3		 In this talk, we introduce the paper “Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology” by Je... [more] ISEC2019-3
p.5
HWS, VLD 2019-02-28
16:45		 Okinawa Okinawa Ken Seinen Kaikan Fundamental Study on Individual Identification Method of Electronic Device Using Difference of Radiation Spectrum Caused by Manufacturing/Mounting Variations
Shugo Kaji (NAIST), Masahiro kinugawa (NIT), Daisuke Fujimoto (NAIST), Laurent Sauvage, Jean-Luc Danger (Telecom ParisTech), Yu-ichi Hayashi (NAIST) VLD2018-120 HWS2018-83		 There is a possibility that electronic devices which contain counterfeited/cloned ICs or electronic components cause ser... [more] VLD2018-120 HWS2018-83
pp.163-167
HWS
(2nd)		 2017-06-12
16:50		 Aomori Hirosaki University Ultra-Light-Weight Implementation of PRINCE Cryptographic Processor
Kohei Matsuda, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Shivam Bashin (Nanyang Tech. Univ.), Ville Yli-Mayry, Naofumi Homma (Tohoku Univ.), Yves Mathieu, Tarik Graba, Jean-Luc Danger (Telecom ParisTech) 		(Advance abstract in Japanese is available) [more]
EMCJ, IEE-EMC 2014-06-20
10:35		 Hyogo Kobe Univ. Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Yu-ichi Hayashi, Naofumi Homma (Tohoku Univ.), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech) EMCJ2014-10		 Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths... [more] EMCJ2014-10
pp.1-6
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