Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SCE |
2024-01-23 15:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo, Online) (Primary: On-site, Secondary: Online) |
[Invited Talk]
Development of semiconductor qubit simulator based on TCAD technology Hidehiro Asai, Shota Iizuka, Tohru Mogami, Junichi Hattori, Koichi Fukuda, Tsutomu Ikegami, Kimihiko Kato, Hiroshi Oka, Takahiro Mori (AIST) |
[more] |
|
SDM |
2023-11-09 15:55 |
Tokyo |
(Tokyo, Online) (Primary: On-site, Secondary: Online) |
[Invited Talk]
Development of Quantum Device Simulator toward Large-Scale Integration of Silicon Qubits Hidehiro Asai, Shota Iizuka, Tohru Mogami, Junichi Hattori, Koichi Fukuda, Tsutomu Ikegami, Kimihiko Kato, Hiroshi Oka, Takahiro Mori (AIST) SDM2023-67 |
[more] |
SDM2023-67 pp.20-25 |
ICD, SDM, ITE-IST [detail] |
2022-08-09 11:50 |
Online |
(Online) |
TCAD analysis of threshold voltage increase of short-channel MOSFET in cryogenic operation Hidehiro Asai, Takumi Inaba, Junichi Hattori, Koichi Fukuda, Hiroshi Oka, Takahiro Mori (AIST) SDM2022-47 ICD2022-15 |
[more] |
SDM2022-47 ICD2022-15 pp.60-63 |
SDM |
2021-11-12 11:30 |
Online |
Online (Online) |
[Invited Talk]
Modeling of Temperature Dependent Mobility of GaN HEMTs by Cellular Automaton Koichi Fukuda, Junichi Hattori, Hidehiro Asai (AIST), Yaita Junya, Junji Kotani (Fujitsu) SDM2021-62 |
A cellular automaton method is applied to temperature-dependent mobility modeling of GaN HEMT. The method utilizes numer... [more] |
SDM2021-62 pp.47-52 |
SDM, ICD, ITE-IST [detail] |
2021-08-17 10:15 |
Online |
Online (Online) |
[Invited Talk]
Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers Shota Iizuka, Kimihiko Kato, Atsushi Yagishita, Hidehiro Asai, Tetsuya Ueda, Hiroshi Oka, Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Takahiro Mori (AIST) SDM2021-30 ICD2021-1 |
We propose a buried nanomagnet (BNM) realizing high-speed/low-variability silicon spin qubit operation, inspired by buri... [more] |
SDM2021-30 ICD2021-1 pp.1-6 |
SDM |
2019-11-08 09:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Device Simulation of Dynamic Behavior of Ferroelectric Field-Effect Transistors Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Hiroyuki Ota, Shinji Migita, Hidehiro Asai (AIST) SDM2019-74 |
We propose a method to simulate the dynamic behavior of field-effect transistors (FETs) having ferroelectric materials i... [more] |
SDM2019-74 pp.27-32 |
SDM |
2019-01-29 09:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Multidomain Dynamics of Ferroelectric Polarization in Negative Capacitance State and its Impacts on Performances of Field-Effect Transistors Hiroyuki Ota, Tsutomu Ikegami, Koichi Fukuda, Junichi HattoriI, Hidehiro Asai, Kazuhiko Endo, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2018-81 |
In this paper, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Eff... [more] |
SDM2018-81 pp.1-4 |
SDM |
2018-11-09 14:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Device Simulation of Field-Effect Transistor Using Ferroelectric Negative Capacitance Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Hiroyuki Ota, Shinji Migita, Hidehiro Asai (AIST) SDM2018-74 |
We consider the method to simulate negative-capacitance field-effect transistors (NC FETs) harnessing negative capacitan... [more] |
SDM2018-74 pp.47-52 |
SDM |
2018-01-30 11:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Perspective of Negative Capacitance FinFETs Investigated by Transient TCAD Simulation Hiroyuki Ota, Shinji Mgita, Tsutomu Ikegami, Junichi Hattori, Hidehiro Asai, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2017-91 |
[more] |
SDM2017-91 pp.1-4 |
SDM |
2017-11-09 15:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
GaN MOS capacitance simulation considering deep traps Koichi Fukuda, Hidehiro Asai, Junichi Hattori, Mitsuaki Shimizu (AIST), Tamotsu Hashizume (Hokkaido Univ.) SDM2017-66 |
Transient mode device simulation is applied to obtain capacitances of GaN MOS capacitors including deep level traps, and... [more] |
SDM2017-66 pp.27-32 |
SDM |
2017-02-06 13:35 |
Tokyo |
Tokyo Univ. (Tokyo) |
[Invited Talk]
Electrical coupling of stacked transistors in monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness Junichi Hattori, Koichi Fukuda, Toshifumi Irisawa, Hiroyuki Ota, Tatsuro Maeda (AIST) SDM2016-143 |
We study the electrical coupling of stacked transistors in monolithic three-dimensional (3D) inverters and investigate i... [more] |
SDM2016-143 pp.23-28 |
SDM |
2017-01-30 10:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology Takahiro Mori, Hidehiro Asai, Junichi Hattori, Koichi Fukuda, Shintaro Otsuka, Yukinori Morita, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Wataru Mizubayashi, Hiroyuki Ota, Takashi Matuskawa (ANational Institute of Advanced Industrial ScieIST) SDM2016-130 |
We improved the performance of a complementary circuit comprising Si-based tunnel field-effect transistors (TFETs) by us... [more] |
SDM2016-130 pp.1-4 |
SDM |
2017-01-30 11:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration Hiroyuki Ota, Tsutomu Ikegami, Junichi Hattori, Koichi Fukuda, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-133 |
Subthreshold operation of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly d... [more] |
SDM2016-133 pp.13-16 |
SDM |
2016-06-29 10:40 |
Tokyo |
Campus Innovation Center Tokyo (Tokyo) |
[Invited Lecture]
Design of SOI-FETs for Steep Slope Switching using Negative Capacitance in Ferroelectric Gate Insulators Hiroyuki Ota, Shinji Migita, Junichi Hattori, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-34 |
This paper discusses a design of fully depleted silicon-on-insulator field-effect transistors with ferroelectric gate in... [more] |
SDM2016-34 pp.9-13 |