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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, IPSJ-SLDM |
2008-05-09 13:55 |
Hyogo |
Kobe Univ. |
A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
[more] |
VLD2008-11 pp.25-30 |
ICD, ITE-CE |
2007-12-13 17:15 |
Kochi |
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A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing Yuichiro Murachi, Junichi Miyakoshi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-128 |
This paper describes a unique SRAM architecture for super-parallel video processing. It features one cycle functional ac... [more] |
ICD2007-128 pp.47-52 |
ICD |
2007-04-12 13:50 |
Oita |
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A Novel Two-Port SRAM for Low Bitline Power Using Majority Logic and Data-Bit Reordering Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-7 |
[more] |
ICD2007-7 pp.35-40 |
ICD, SDM |
2006-08-18 15:00 |
Hokkaido |
Hokkaido University |
A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment Hiroki Noguchi (Kobe Univ.), Yasuhiro Morita (Kanazawa Univ.), Hidehiro Fujiwara, Kentaro Kawakami, Junichi Miyakoshi (Kobe Univ.), Shinji Mikami (Kanazawa Univ.), Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
[more] |
SDM2006-152 ICD2006-106 pp.155-160 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-20 13:40 |
Miyagi |
Ichinobo, Sakunami-Spa |
A low power H.264 motion estimation algorithm for mobile video applications Masaki Hamamoto, Kenichi Nagai (Kobe Univ.), Tetsuro Matsuno (Kanazawa Univ.), Yuichiro Murachi, Junichi Miyakoshi (Kobe Univ.), Masayuki Miyama (Kanazawa Univ.), Masahiko Yoshimoto (Kobe Univ.) |
H.264 employs variable block size motion compensation which supports 7 block sizes from 16x16 to 4x4. This feature enhan... [more] |
SIP2005-107 ICD2005-126 IE2005-71 pp.67-72 |
ICD, SDM |
2005-08-18 08:30 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application Yuichiro Murachi (Kobe Univ.), Koji Hamano, Tetsuro Matsuno (Kanazawa Univ.), Junichi Miyakoshi (Kobe Univ.), Masayuki Miyama (Kanazawa Univ.), Masahiko Yoshimoto (Kobe Univ.) |
This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video applicat... [more] |
SDM2005-128 ICD2005-67 pp.1-6 |
ICD |
2005-05-26 10:00 |
Hyogo |
Kobe Univ. |
A Low-power Systolic Array Architecture for Block-matching Motion Estimation Junichi Miyakoshi, Yuichiro Murachi (Kobe Univ.), Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto (Kanazawa Univ.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-20 pp.1-6 |
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