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Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
11:20		 Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)		 Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder
Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU) VLD2022-58 RECONF2022-81		 The SA method is widely used as a logic device placement method for FPGAs. We have introduced neural networks to the pla... [more] VLD2022-58 RECONF2022-81
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