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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, ITE-CE |
2007-12-14 14:40 |
Kochi |
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A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] |
ICD2007-138 pp.107-111 |
CPSY |
2007-10-25 13:00 |
Kumamoto |
Kumamoto University |
The application of the massively parallel processor based on the matrix architecture Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24 |
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] |
CPSY2007-24 pp.1-5 |
CPSY |
2007-10-25 13:40 |
Kumamoto |
Kumamoto University |
The program development method of the massively parallel processor based on the matrix architecture. Hiroyuki Yamasaki, Katsuya Mizumoto, Hideyuki Noda, Tetsu Nishijima, Kanako Yoshida, Takeaki Sugimura, Takashi Kurafuji, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-25 |
Recently, the installed applications in the digital devices has been remarkably progressed. Considering these background... [more] |
CPSY2007-25 pp.7-12 |
ICD, SDM |
2006-08-17 09:05 |
Hokkaido |
Hokkaido University |
A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture Tetsushi Tanizaki, Takayuki Gyohten, Hideyuki Noda, Masami Nakajima, Katsuya Mizumoto, Katsumi Dosaka (Renesas) |
A super parallel SIMD processor based on the matrix architecture which consists of 2k processors, embedded SRAM, and tim... [more] |
SDM2006-125 ICD2006-79 pp.1-6 |
RECONF |
2005-05-13 14:30 |
Kyoto |
Kyoto University |
A high-speed real number computation using simple SIMD operations Hiroyuki Yamasaki, Masahiro Iida (Kumamoto Univ.), Katsuya Mizumoto, Osamu Yamamoto (Renesas), Toshinori Sueyoshi (Kumamoto Univ.) |
We research the speed-up of application in the embedded system with consideration of cost and power
consumption. This p... [more] |
RECONF2005-23 pp.49-54 |
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