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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 19 of 19  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2022-06-08
11:35
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Introduction of Power Monitoring Tool for FPGA Clusters and Power Analysis of FPGA Clusters
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ) RECONF2022-18
Low power consumption is a significant advantage of FPGA clusters.
This study reports the detailed power consumption an... [more]
RECONF2022-18
pp.80-85
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-02
09:20
Online Online The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44
We are currently developing a multi-FPGA system, Flow-in-Cloud (FiC) system. FiC directly interconnects multiple middle-... [more] VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44
pp.111-116
RECONF 2021-09-10
16:10
Online Online Multi-FPGA Based Hardware Acceleration for Genetic Data Analysis
Imdad Ullah (Keio Univ.), Akram Ben Ahmed (AIST), Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) RECONF2021-24
 [more] RECONF2021-24
pp.42-47
CPSY, DC, IPSJ-ARC [detail] 2021-07-20
15:15
Online Online CPSY2021-3 DC2021-3  [more] CPSY2021-3 DC2021-3
pp.13-18
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
16:00
Online Online Implementation of Versatile Tensor Accelarator (VTA) on the Flow-in-Cloud FPGA system
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) CPSY2020-69 DC2020-99
 [more] CPSY2020-69 DC2020-99
pp.115-120
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-26
10:30
Online Online VLD2020-58 CPSY2020-41 RECONF2020-77 (To be available after the conference date) [more] VLD2020-58 CPSY2020-41 RECONF2020-77
pp.107-112
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
11:00
Online Online The next generation FiC with M-KUBOS board
Hideharu Amano, Kazuei Hironaka, Kensuke Iizuka (Keio Univ.) CPSY2020-9 DC2020-9
 [more] CPSY2020-9 DC2020-9
pp.55-60
RECONF 2020-05-29
14:40
Online Online RECONF2020-16  [more] RECONF2020-16
pp.85-90
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
14:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University Implementation and Evaluation of a Router on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2019-59 CPSY2019-57 RECONF2019-49
The trade-off between power efficiency and performance is important in large-scale computing systems like a datacenter. ... [more] VLD2019-59 CPSY2019-57 RECONF2019-49
pp.31-36
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
14:45
Kanagawa Raiosha, Hiyoshi Campus, Keio University Performance Evaluation of Using Multi-Switch on a Multi-FPGA System
Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2019-60 CPSY2019-58 RECONF2019-50
Flow-in-Cloud(FiC) is a system which consists of multiple middle-range FPGAs connected by high-speed serial links, and i... [more] VLD2019-60 CPSY2019-58 RECONF2019-50
pp.37-42
DC, CPSY, IPSJ-ARC [detail] 2019-06-11
14:10
Kagoshima National Park Resort Ibusuki Data Compression System of Storage Compatible with High Performance and High Compression Rate
Yusuke Yamaga, Takaki Matsushita, Kazuei Hironaka, Tomohiro Kawaguchi (Hitachi) CPSY2019-2 DC2019-2
In recent years, the amount of data handled by information systems is increasing explosively. In order to store huge amo... [more] CPSY2019-2 DC2019-2
pp.27-32
RECONF 2018-09-18
10:50
Fukuoka LINE Fukuoka Cafe Space
Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano (Keio Univ.) RECONF2018-29
(To be available after the conference date) [more] RECONF2018-29
pp.55-59
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2018-07-31
09:30
Kumamoto Kumamoto City International Center CPSY2018-16  [more] CPSY2018-16
pp.65-69
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-24
09:00
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan Deduplication Estimation System for Large Scale Enterprise Storage
Kazuei Hironaka, Tomohiro Kawaguchi (Hitachi) CPSY2017-10 DC2017-10
In recent years, the amount of data handled by enterprise information systems is explodingly increasing.
In order to ... [more]
CPSY2017-10 DC2017-10
pp.51-54
RECONF 2012-05-29
10:35
Okinawa Tiruru (Naha Okinawa, Japan) A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array
Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2012-4
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use P... [more] RECONF2012-4
pp.19-24
RECONF 2011-09-26
11:35
Aichi Nagoya Univ. Low Power Dynamically Reconfigurable Processor with Dual-Vdd/Dual-Vth and its Optimization
Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2011-24
 [more] RECONF2011-24
pp.13-18
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
14:10
Kanagawa Keio Univ (Hiyoshi Campus) Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61
This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] VLD2010-92 CPSY2010-47 RECONF2010-61
pp.49-54
RECONF 2010-09-17
11:25
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration
Masayuki Kimura, Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2010-35
 [more] RECONF2010-35
pp.103-108
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
09:00
Kanagawa Keio Univ (Hiyoshi Campus) A study of software development environment for dynamic-reconfigurable processor MuCCRA-3.
Kazuei Hironaka, Katsunobu Nishimura (Tokai Univ.), Hideharu Amano (Keio Univ.) VLD2009-69 CPSY2009-51 RECONF2009-54
The dynamic-reconfigurable processor is consisted of many small and simple processing units. This processor is
able to ... [more]
VLD2009-69 CPSY2009-51 RECONF2009-54
pp.1-6
 Results 1 - 19 of 19  /   
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