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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HCGSYMPO (2nd) |
2024-12-11 - 2024-12-13 |
Ishikawa | The Kanazawa Theatre | Evaluation of EEG rhythm for the fluctuation of daily mood states Kazuki Inoue, Masahiro Kawasaki (Tsukuba Univ.) |
(To be available after the conference date) [more] | |
| ITE-HI, IE, ITS, ITE-MMS, ITE-ME, ITE-AIT [detail] | 2020-02-27 10:45 |
Hokkaido | Hokkaido Univ. (Cancelled but technical report was issued) |
Generation of Hiragana Ambigram Based on Character Structure Characteristics Kazuki Inoue, Hiroki Takahashi (UEC) |
An ambigram is a word which can be also read from a different direction. Generation of ambigrams, however, requires not ... [more] | |
| WIT, SP | 2017-10-20 11:50 |
Fukuoka | Tobata Library of Kyutech (Kitakyushu) | Study of Assessment Support System of Unilateral Spatial Neglect Makoto Fujimura, Kazuki Inoue, Akira Fuii, Toshio Higashi (Nagasaki Univ.)  SP2017-53 WIT2017-49 |
Unilateral spatial neglect (USN) is one of the after effects of the stroke. USN is a lack of awareness, or decreased awa... [more] | SP2017-53 WIT2017-49 pp.107-111 |
| RECONF | 2013-05-21 11:25 |
Kochi | Kochi Prefectural Culture Hall | A defect-robust FPGA-IP core architecture Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-13 |
In this paper, we propose fault-tolerant FPGA -IP cores for system LSI. Unlike discrete FPGAs, in which the integration... [more] |
RECONF2013-13 pp.67-72 |
| RECONF | 2012-09-18 15:15 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | An Area Minimized Logic Cluster using COGRE Logic Cell Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-32 |
These days, FPGAs (Field Programmable Gate Arrays) is required to increase in size and performance in order to deal w... [more] |
RECONF2012-32 pp.49-54 |
| RECONF | 2012-09-19 13:15 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | A Design Framework for Reconfigurable IPs with VLSI CADs Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-41 |
The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps... [more] | RECONF2012-41 pp.101-106 |
| RECONF | 2012-05-29 16:00 |
Okinawa | Tiruru (Naha Okinawa, Japan) | An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-13 |
FPGA's fault detection needs a great deal of test time as compared with ASIC because FPGAs have complex structures and p... [more] | RECONF2012-13 pp.71-76 |
| RECONF | 2011-09-26 13:30 |
Aichi | Nagoya Univ. | A Novel Cluster Structure based on Input Sharing of LUTs Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-25 |
Cluster-based FPGAs are composed of logic clusters having LUTs which are basic logic elements. At each of logic cluster... [more] |
RECONF2011-25 pp.19-24 |
| RECONF | 2011-05-13 13:55 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | A Homogeneous Routing Architecture for Efficient FPGA Design Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-19 |
In previous work, we have designed a prototype chip of island-style FPGA architecture. This architecture has very comple... [more] | RECONF2011-19 pp.109-114 |
| CAS | 2011-01-25 14:10 |
Kumamoto | Kumamoto University | A design of FPGA routing structure with Switch-Block-cum-Shifter Komei Yoshizawa, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CAS2010-88 |
In conventional FPGA(Field Programmable Gate Array), programmable innterconects have great impacts on delay and area. Th... [more] | CAS2010-88 pp.23-28 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 11:35 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology Hiroki Yosho, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2010-105 CPSY2010-60 RECONF2010-74 |
In general, an ATPG(Automatic Test Pattern Generation) is used to test LSI. However, because logic function and wiring r... [more] | VLD2010-105 CPSY2010-60 RECONF2010-74 pp.145-150 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 14:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Design of Reconfigurable Logic Device based on Variable Grain Logic Cell Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-79 CPSY2009-61 RECONF2009-64 |
We propose a variable grain logic cell（VGLC）architecture. Its key feature is variable granularity which helps to create ... [more] | VLD2009-79 CPSY2009-61 RECONF2009-64 pp.59-64 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka | Kitakyushu Science and Research Park | A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-42 pp.21-26 |
| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33 |
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained types, its structure can ... [more] |
RECONF2007-33 pp.7-12 |
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