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All Technical Committee Conferences (Searched in: Recent 10 Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
MRIS, ITE-MMS |
2018-07-06 16:35 |
Tokyo |
Waseda Univ. (Tokyo) |
Ultra-high-efficient Writing in Voltage-Control Spintronics Memory(VoCSM) Altansargai Buyandalai, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi, Yuichi Ohsawa, Naoharu Shimomura, Satoshi Shirotori, Hideyurki Sugiyama, Yushi Kato, Mizue Ishikawa, Katsuhiko Koi, Soichi Oikawa, Kazutaka Ikegami, Satoshi Takaya, Shinobu Fujita, Atsushi Kurobe (Toshiba Corporation) |
[more] |
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ICD |
2017-04-20 10:10 |
Tokyo |
(Tokyo) |
[Invited Lecture]
Voltage-Control Spintronics Memory(VoCSM) Having Potentials of Ultra-Low Energy-Consumption and High-Density Hiroaki Yoda, Naoharu Simomura, Yuichi Osawa, Satoshi Shiratori, Yushi Kato, Iguchi Tomoaki, Yuzou Kamiguchi, Buyandalai Altansargai, Yoshiaki Saito, Katsuhiko Koi, Sugiyama Hideyuki, Souichi Oikawa, Shimizu Mariko, Miaue Ishikawa, Kazutaka Ikegami (Toshiba) ICD2017-1 |
[more] |
ICD2017-1 pp.1-4 |
SDM |
2017-01-30 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135 |
In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover... [more] |
SDM2016-135 pp.21-24 |
SDM |
2016-01-28 15:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] |
SDM2015-126 pp.27-30 |
ICD |
2015-04-17 12:40 |
Nagano |
(Nagano) |
[Invited Talk]
Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10 |
[more] |
ICD2015-10 pp.45-50 |
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