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All Technical Committee Conferences (Searched in: Recent 10 Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2025-02-18 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A C-Element-Based Latch Design for Flip-Flops with Complete SNU and Partial DNU Tolerance and Enhanced Soft Error Resilience Around Clock Edges Song Wang, Kazuteru Namba (Chiba Univ)  DC2024-113 |
[more] | DC2024-113 pp.43-46 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-12 16:25 |
Oita | COMPAL HALL (Primary: On-site, Secondary: Online) |
Design of SNU-tolerant non-volatile Flip-Flop Kyotaro Takahashi, Kazuteru Namba (Chiba Univ.) VLD2024-40 ICD2024-58 DC2024-62 RECONF2024-70 |
In recent years, the soft error rate in VLSI has been increasing due to miniaturization. Soft errors are temporary error... [more] | VLD2024-40 ICD2024-58 DC2024-62 RECONF2024-70 pp.79-83 |
| CPSY, DC, RECONF, IPSJ-ARC [detail] | 2024-08-09 17:25 |
Tokushima | Awagin Hall (Primary: On-site, Secondary: Online) |
TMR/DMR adaptive soft-error tolerant redundant system using FPGA cluster Homu Omura, Kazuteru Namba (Chiba Univ.) CPSY2024-39 DC2024-39 RECONF2024-39 |
In recent years, the probability of soft error occurrence has increased due to the miniaturization of semiconductor devi... [more] | CPSY2024-39 DC2024-39 RECONF2024-39 pp.130-134 |
| CPSY, DC, RECONF, IPSJ-ARC [detail] | 2024-06-11 10:45 |
Yamanashi | Isawa View Hotel (Primary: On-site, Secondary: Online) |
Fault classification and prediction of AI accelerators based on activation maximization Ma Shanmou, Kazuteru Namba (Chiba Univ.) CPSY2024-8 DC2024-8 RECONF2024-8 |
This research proposes a method based on neural network interpretability techniques to effectively classify and predict ... [more] | CPSY2024-8 DC2024-8 RECONF2024-8 pp.40-45 |
| CPSY, DC, RECONF, IPSJ-ARC [detail] | 2024-06-11 13:15 |
Yamanashi | Isawa View Hotel (Primary: On-site, Secondary: Online) |
Burst Length Optimization in MLC PCM using Encoding and Merge Sort Jin Lei, Kazuteru Namba (Chiba Univ.) CPSY2024-10 DC2024-10 RECONF2024-10 |
In recent years, with the development of fields such as big data, artificial intelligence (AI), and the Internet of Thin... [more] | CPSY2024-10 DC2024-10 RECONF2024-10 pp.52-57 |
| DC | 2024-02-28 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | System design using DICE-based edge-triggered soft-error-tolerant D-FF Kazuteru Namba (Chiba Univ.) DC2023-95 |
The recent miniaturization of VLSI has made the effects of radiation-induced soft errors more serious. From this, many... [more] |
DC2023-95 pp.7-10 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 15:55 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
WGAN-GP based AI accelerator fault detection and fault classification analysis Shuming Xu, Kazuteru Namba (Chiba Univ.) VLD2023-59 ICD2023-67 DC2023-66 RECONF2023-62 |
[more] | VLD2023-59 ICD2023-67 DC2023-66 RECONF2023-62 pp.150-155 |
| SANE | 2023-11-13 13:05 |
Chiba | Chiba Univ. (Nishi-Chiba Campus) (Primary: On-site, Secondary: Online) |
Board design of digital chirp generator using FPGA Yoshiaki Saito, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ.) SANE2023-52 |
Remote sensing, which enables observation of an object without touching it, has been widely used for earth observation i... [more] | SANE2023-52 pp.28-33 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-03 11:45 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Design of soft-error tolerant non-volatile flip-flops Shogo Takahashi, Kazuteru Namba (Chiba Univ.) CPSY2023-13 DC2023-13 |
In recent years，the incidence of soft errors in VLSI has been increasing due to miniaturization，higher integration，and l... [more] | CPSY2023-13 DC2023-13 pp.31-36 |
| DC | 2022-12-16 14:10 |
Yamaguchi | (Primary: On-site, Secondary: Online) |
Stuck-at Fault Tolerance in DNN Using Outliers and Sampling Tomohiro Ishii, Kazuteru Namba (Chiba Univ.) DC2022-75 |
The development of artificial intelligence and the expansion of big data have led to the implementation of neural networ... [more] | DC2022-75 pp.17-20 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 15:25 |
Kumamoto | (Primary: On-site, Secondary: Online) |
A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage Ruoxi Yu, Kazuteru Namba (Chiba Univ.) VLD2022-24 ICD2022-41 DC2022-40 RECONF2022-47 |
With advances in artificial intelligence and machine learning technologies, many deep learning applications are being de... [more] | VLD2022-24 ICD2022-41 DC2022-40 RECONF2022-47 pp.31-36 |
| SANE | 2022-11-10 13:50 |
Chiba | Chiba Univ. (Nishi-Chiba Campus) (Primary: On-site, Secondary: Online) |
Development of CP-SAR image processing system using high-level synthesis Takumi Aoyama, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ.) SANE2022-56 |
(To be available after the conference date) [more] | SANE2022-56 pp.35-38 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-10-11 16:15 |
Niigata | Yuzawa Toei Hotel (Primary: On-site, Secondary: Online) |
Low power quantized neural network by reducing the operating voltage of SRAM Ji Wu, Kazuteru Namba (Chiba Univ) CPSY2022-20 DC2022-20 |
With the advancement of artificial intelligence technologies, neural networks have been attracting attention as a machin... [more] | CPSY2022-20 DC2022-20 pp.14-19 |
| SANE | 2021-12-16 14:55 |
Chiba | Chiba University (Primary: On-site, Secondary: Online) |
Comparison of HLS and IP core for CP-SAR images processing onboard UAV Yuta Tanaka, Takumi Aoyama, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ) SANE2021-76 |
(To be available after the conference date) [more] | SANE2021-76 pp.75-78 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 11:35 |
Online | Online | Low power neural network by reducing the operating voltage of SRAM Keisuke Kozu, Kazuteru Namba (Chiba Univ.) VLD2021-25 ICD2021-35 DC2021-31 RECONF2021-33 |
With the advancement of machine learning technology, networks are becoming more and more complex and computationally int... [more] | VLD2021-25 ICD2021-35 DC2021-31 RECONF2021-33 pp.49-53 |
| DC, CPSY, IPSJ-ARC [detail] | 2021-10-11 16:00 |
Online | Online | Edge triggered D Flip-Flop using complementarity of DICE Noriki Matsuura, Kazuteru Namba (Chiba Univ.) CPSY2021-15 DC2021-15 |
In recent years, the probability of soft errors has been increasing due to the miniaturization, high integration, and lo... [more] | CPSY2021-15 DC2021-15 pp.19-24 |
| CPSY, DC, IPSJ-ARC [detail] | 2021-07-20 12:00 |
Online | Online | Content addressable memory using multi-level cell phase-change memory Tomohiro Takahashi, Kazuteru Namba (Chiba Univ.) CPSY2021-1 DC2021-1 |
[more] | CPSY2021-1 DC2021-1 pp.1-6 |
| SANE | 2020-11-25 14:15 |
Online | Online | Design of CP-SAR image processing system board using FPGA Motoharu Muroga, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ.) SANE2020-34 |
We are conducting an experiment for Circularly Polarized Synthetic Aperture Radar (CP-SAR) using Unmanned Aerial Vehicle... [more] | SANE2020-34 pp.43-47 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 10:55 |
Online | Online | DET Flip-Flops with SEU Detection Capability Using DICE and C-Element Xu Haijia, Kazuteru Namba (Chiba Univ.) VLD2020-14 ICD2020-34 DC2020-34 RECONF2020-33 |
Abstract A dual-edge-triggered flip-flop (DET-FF) composed of DICE latch (Dual Interlocked Storage Cell) and C-element ... [more] | VLD2020-14 ICD2020-34 DC2020-34 RECONF2020-33 pp.18-23 |
| DC, CPSY, IPSJ-ARC [detail] | 2020-10-12 14:10 |
Online | Online | Soft error tolerant SR latch using C-element Ibuki Nakata, Kazuteru Namba (Chiba Univ) CPSY2020-19 DC2020-19 |
VLSI systems have become downsized, high integrated and low-power. As a result, the incidence of soft errors is increasi... [more] | CPSY2020-19 DC2020-19 pp.12-15 |
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