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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
NS, IN
(Joint)		 2024-03-01
13:50		 Okinawa Okinawa Convention Center Two-Level Detection Method of DDoS Attack Mimicking CDN Caches
Kazuya Taniguchi, Noriaki Kamiyama (Ritsumeikan Univ) NS2023-222		  [more] NS2023-222
pp.294-299
VLD, HWS, ICD 2024-02-28
15:55		 Okinawa
(Primary: On-site, Secondary: Online)		 Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat) VLD2023-103 HWS2023-63 ICD2023-92		 In this paper, for a three-layer bottleneck channel routing problem in which pins of each net are placed on the upper or... [more] VLD2023-103 HWS2023-63 ICD2023-92
pp.24-29
HWS, VLD 2023-03-03
09:55		 Okinawa
(Primary: On-site, Secondary: Online)		 Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) VLD2022-101 HWS2022-72		 Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2022-101 HWS2022-72
pp.149-154
VLD, HWS [detail] 2022-03-07
09:35		 Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54		 Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
pp.7-12
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