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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-24 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An FPGA implementation of arc-sine high-radix CORDIC algorithm Hiroshi Matsuoka, Naofumi Takagi (Kyoto Univ.), Kazuyoshi Takagi (Mie Univ.)  VLD2019-86 CPSY2019-84 RECONF2019-76 |
We consider the realization of the circuit on the FPGA based on the high radix CORDIC algorithm that we proposed for cal... [more] | VLD2019-86 CPSY2019-84 RECONF2019-76 pp.193-197 |
| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
A Routing Method with Wire Length Matching for RSFQ Logic Circuits Using Thin PTLs Kei Kitamura (Kyoto Univ), Kazuyoshi Takagi (Mie Univ), Naofumi Takagi (Kyoto Univ) SCE2019-35 |
A routing method with wire length matching using thin PTLs for RSFQ circuits is proposed. For AIST-ADP2 fabrication tech... [more] | SCE2019-35 pp.23-25 |
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| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
A Comparison of Clocking Schemes for SFQ Circuits Takahiro Kawaguchi (Kyoto Univ.), Kazuyoshi Takagi (Mie Univ.), Takagi Naofumi (Kyoto Univ.) SCE2019-36 |
[more] | SCE2019-36 pp.27-32 |
|
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 15:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An integrated development platform of FPGA for ROS-based autonomous mobile robot Sou Tamura, Yasuhiro Nitta, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ) VLD2018-79 CPSY2018-89 RECONF2018-53 |
[more] | VLD2018-79 CPSY2018-89 RECONF2018-53 pp.43-48 |
| SANE | 2018-11-08 14:10 |
Overseas | China (Xuchang) | Imaging Performance of Millimeter Wave SAR for Portable Weapon Detection Koki Homma, Hiroyoshi Yamada, Ryoichi Sato, Yoshio Yamaguchi (Niigata Univ.), Hiroki Mori (Toshiba), Kazuyoshi Takagi, Hironori Dobashi, Yasushi Murakami (Toshiba Infrastructure Systems & Solutions) SANE2018-58 |
Concealed weapon detection by electromagnetic wave have been attracting attention recently. Currently, several products ... [more] | SANE2018-58 pp.17-20 |
| RECONF | 2018-05-24 14:55 |
Tokyo | GATE CITY OHSAKI | An feasibility study of an automatic selection method for SW/HW communication interface in SWORDS framework Yasuhiro Nitta, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) RECONF2018-8 |
[more] | RECONF2018-8 pp.39-44 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 13:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Calculation method of exponential function on FPGAs using high-radix STL method Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) RECONF2017-46 |
We propose the calculation method of double precision floating point exponential function for FPGA with correct rounding... [more] | RECONF2017-46 pp.55-59 |
| SCE | 2017-04-21 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An RSFQ Pattern Matching Circuit Based on Systolic Architecture Kazuyoshi Takagi, Masaya Ohata, Naofumi Takagi (Kyoto Univ.) SCE2017-7 |
We propose a regular expression pattern matching circuit using rapid single flux quantum (RSFQ) circuit. Proposed circu... [more] |
SCE2017-7 pp.35-39 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-10 14:50 |
Okinawa | Kumejima Island | Double-precision floating-point logarithm calculation method for FPGA Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) CPSY2016-156 DC2016-102 |
Floating-point arithmetic standard IEEE 754 was revised in 2008, and it presents 36 functions that should be calculated ... [more] | CPSY2016-156 DC2016-102 pp.363-367 |
| SCE | 2016-04-20 14:40 |
Tokyo | On-chip Implementation of Random-Access-Memory and RSFQ Microprocessor with High-Functionality Ryo Sato (Nagoya Univ.), Yuki Ando (Kyoto Univ.), Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) SCE2016-5 |
The single flux quantum (SFQ) microprocessor demonstrated so far was not able to run meaningful programs due to the limi... [more] | SCE2016-5 pp.25-30 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Software-Oriented Design and Synthesis Platform for a Construction of Real-Time Systems on Programmable SoCs Takuya Hatayama, Yusuke Tani, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) RECONF2015-53 |
We have been developing SWORDS platform, a SoftWare ORiented Design and Synthesis platform.SWORDS platform aims at impro... [more] | RECONF2015-53 pp.27-32 |
| RECONF | 2015-06-20 09:30 |
Kyoto | Kyoto University | A SW/HW Interface Implementation Method in the System Design Environment for Programmable SoCs Yusuke Tani, Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) RECONF2015-14 |
A programmable SoC, which integrates processors and FPGA on the same chip, has become attracted attention in embedded sy... [more] | RECONF2015-14 pp.73-78 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75 |
In recent years, high speed and high precision computing is increasingly needed. Hardware support for IEEE754 compliant... [more] |
CPSY2014-75 pp.19-23 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-76 |
Complex operations are used in scientific computing and signal processing. Floating-point complex multiplication is imp... [more] |
CPSY2014-76 pp.25-29 |
| COMP | 2014-09-02 11:30 |
Aichi | Toyohashi University of Technology | On the number of matrix multiplications in the evaluation of the matrix polynomial I+A+A^2+...+A^{N-1} Kotaro Matsumoto, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) COMP2014-18 |
[more] | COMP2014-18 pp.23-27 |
| SCE | 2014-07-23 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design and Evaluation of the 4-Bit Parallel Bit-Slice-ALU Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.), Tang Gaung-Ming, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) SCE2014-25 |
[more] | SCE2014-25 pp.7-12 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 15:30 |
Nagasaki | Evaluation Environment for Configuration of Floating-Point Unit Arrays Yuya Itoh, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) CPSY2012-94 DC2012-100 |
A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent archi... [more] | CPSY2012-94 DC2012-100 pp.253-258 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 10:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A speculative execution method for indefinite loops in high level synthesis Tatsuma Araki, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ) VLD2012-76 DC2012-42 |
[more] | VLD2012-76 DC2012-42 pp.99-104 |
| SCE | 2012-07-19 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | SFQ Bit-Slice Floating Point Adder Yukio Ohmomo, Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) SCE2012-11 |
Single Flux Quantum (SFQ) circuits operate at high-speed with low-power consumption. A Large-Scale Reconfigurable Data ... [more] |
SCE2012-11 pp.13-17 |
| VLD | 2012-03-06 15:30 |
Oita | B-con Plaza | CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-129 |
In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the proble... [more] | VLD2011-129 pp.55-60 |
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