Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2017-03-10 17:00 |
Okinawa |
Kumejima Island |
A Scalable Data Centric Converged System for Big Data Analytics Yuki Sasaki, Kenji Takahashi, Keishi Sakanushi, Atsuhiro Kinoshita (Toshiba) CPSY2016-162 DC2016-108 |
Data analytics for IoT market is the most important issue today. Data needs to be converted to relevant information in a... [more] |
CPSY2016-162 DC2016-108 pp.399-404 |
VLD |
2014-03-04 15:05 |
Okinawa |
Okinawa Seinen Kaikan |
Exposure source optimization by clustering for lithography Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-152 |
In lithography, we generate patterns on a wafer through a photomask,
where patterns generated have to be close to ideal... [more] |
VLD2013-152 pp.105-110 |
IPSJ-SLDM, VLD |
2012-05-30 14:30 |
Fukuoka |
Kitakyushu International Conference Center |
Task Allocation Optimization Method Using SA Method to Automatically Set Starting Temperature for Multi-Processor System Yuichiro Yanabu, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2012-1 |
Recently, Multi-Processor System is widely used for huge applications such as image and multimedia processing. To reduce... [more] |
VLD2012-1 pp.1-6 |
VLD, IPSJ-SLDM |
2010-05-20 10:25 |
Fukuoka |
Kitakyushu International Conference Center |
Implementation of error correction method on small area and low power consumption processor for the capsular detrusor pressure measurement system Hiroki Ohsawa, Tomohiro Kondo, Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2010-6 |
Our research group is developing a capsular detrusor pressure measurement system.
In this system, communication errors ... [more] |
VLD2010-6 pp.49-54 |
VLD |
2009-09-25 10:25 |
Osaka |
Osaka University |
Triage Device Slightly Injured Person in Disaster Medical Assistant Network Keishi Sakanushi, Akihito Hiromori (Osaka Univ/JST), Taichiro Imamura, Junya Okamoto (Osaka Univ), Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ/JST), Junji Kitamichi (Osaka Univ), Teruo Higashino (Osaka Univ/JST) VLD2009-37 |
[more] |
VLD2009-37 pp.45-50 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 10:30 |
Fukuoka |
Kitakyushu International Conference Center |
Highly Extensible Base Processors for Short-term ASIP Design Hirofumi Iwato, Takuji Hieda, Hiroaki Tanaka (Osaka Univ.), Jun Sato (Tsuruoka NCT), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2007-92 DC2007-47 |
ASIPs (Application Specific Instruction-set Processors) are embbeded processors
whose architectures are customized for... [more] |
VLD2007-92 DC2007-47 pp.19-24 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 15:45 |
Fukuoka |
Kitakyushu International Conference Center |
Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-104 DC2007-59 |
In recent years, spread of data intensive multimedia applications equires high-performance in embedded systems.
Massiv... [more] |
VLD2007-104 DC2007-59 pp.91-96 |
VLD, IPSJ-SLDM |
2007-05-10 13:30 |
Kyoto |
Kyodai Kaikan |
Memory Assignment Method for Matrix Processing Array Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-1 |
MTA (MaTrix processing Array), which is developed by Renesas Technology Corp., can achieve high performance for digital ... [more] |
VLD2007-1 pp.1-6 |
VLD, IPSJ-SLDM |
2007-05-10 13:55 |
Kyoto |
Kyodai Kaikan |
Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
Partial forwarding is a design method to put forwarding paths on a part of processor pipeline.
To schedule instructions... [more] |
VLD2007-2 pp.7-12 |
VLD, IPSJ-SLDM |
2007-05-10 14:20 |
Kyoto |
Kyodai Kaikan |
Reconfigurable Architecture with Caluculation Function for Shift Keying Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2007-3 |
[more] |
VLD2007-3 pp.13-18 |
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-30 14:20 |
Fukuoka |
Kitakyushu International Conference Center |
Dual Core ASIP for High Speed Image Effect Processing Takahiro Notsu (Osaka Univ.), Tastuhiro Yoshimura (AXELL), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
[more] |
VLD2006-81 DC2006-68 pp.55-60 |
VLD, IPSJ-SLDM |
2006-05-11 16:15 |
Ehime |
Ehime University |
[Invited Talk]
Configurable Processor Design Environment ASIP Meister Masaharu Imai, Ittetsu Taniguchi, Yoshinori Takeuchi, Keishi Sakanushi (Osaka Univ.) |
[more] |
VLD2006-5 pp.25-30 |
RECONF |
2005-05-12 10:30 |
Kyoto |
Kyoto University |
Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
The dynamic reconfigurable processor is a device that can change interconnections between processor elements and process... [more] |
RECONF2005-3 pp.13-18 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 14:40 |
Kanagawa |
|
ASIP Architecture for Real-Time Graphical Effect Acceleration Tatsuhiro Yoshimura, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
Graphical effect processing realizes a variety of
visual representation.
In this paper, we propose an ASIP architectur... [more] |
VLD2004-118 CPSY2004-84 pp.49-54 |
IE, SIP, ICD, IPSJ-SLDM |
2004-10-22 15:50 |
Yamagata |
|
Bus architecture optimization method for IP-based design Kyoko Ueda, Keishi Sakanushi, Noboru Yoneoka, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
In IP-based design, to find the optimal bus architecture is very important problem because bus architecture strongly aff... [more] |
SIP2004-101 ICD2004-133 IE2004-77 pp.73-78 |