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 Results 1 - 20 of 113  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2021-08-18
10:15
Online Online [Invited Talk] Voltage-sensing FeFET CiM with MAC by Source-follower Read and Charge-sharing
Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi (Univ. Tokyo) SDM2021-37 ICD2021-8
An energy-efficient and high-throughput HZO FeFET Computation-in-Memory (CiM) is proposed. The FeFET CiM performs voltag... [more] SDM2021-37 ICD2021-8
pp.38-41
SDM 2021-06-22
16:50
Online Online Application-induced TaOx ReRAM Cell Reliability Variation Tolerated High-speed Storage
Chihiro Matsui, Ken Takeuchi (Univ. Tokyo) SDM2021-27
Storage application induces various types or errors in TaOx ReRAM cells and the storage performance degrades. To improve... [more] SDM2021-27
pp.21-22
SDM 2021-06-22
17:10
Online Online Influence of quantized bit precision and bit-error rate in Computation-in-Memory with ReRAM on optimal answers of combinatorial optimization problems
Naoko Misawa, Kenta Taoka, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi (Univ. Tokyo) SDM2021-28
The knapsack problem, one of combinatorial optimization problems, is solved effectively by simulated annealing in ReRAM ... [more] SDM2021-28
pp.23-26
HWS, VLD [detail] 2020-03-05
15:20
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
[Memorial Lecture] Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance
Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi (Chuo Univ.) VLD2019-119 HWS2019-92
Storage Class Memories (SCMs) are used as non-volatile (NV) cache memory as well as storage. Multi-SCM storage with two ... [more] VLD2019-119 HWS2019-92
pp.145-150
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
14:15
Ehime Ehime Prefecture Gender Equality Center Neural Network-based Lifetime Prediction and Reliability Enhancement Techniques for 3D NAND Flash Memory
Masaki Abe, Ken Takeuchi (Chuo Univ.) ICD2019-30 IE2019-36
NAND flash memories have lifetime such as data-retention time and read cycles. This paper proposes neural network techni... [more] ICD2019-30 IE2019-36
pp.7-12
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
14:40
Ehime Ehime Prefecture Gender Equality Center Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits
Koki Kamimura, Susumu Nohmi, Ken Takeuchi (Chuo Univ.) ICD2019-31 IE2019-37
In recent years, Moore’s Law which has supported the improvement of semiconductor performance is coming to an end. There... [more] ICD2019-31 IE2019-37
pp.13-17
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
15:45
Ehime Ehime Prefecture Gender Equality Center Design of optimal NV-memory configuration for hybrid SSD with QLC NAND flash memory
Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi (Chuo Univ.) ICD2019-41 IE2019-47
In order to expand capacity and reduce cost of NAND flash memory, the number of bits per cell has been increased. Howeve... [more] ICD2019-41 IE2019-47
pp.59-63
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
13:45
Hiroshima Satellite Campus Hiroshima Autonomous SCM capacity adjustment method in SCM/NAND flash hybrid storage
Chihiro Matsui, Ken Takeuchi (Chuo Univ.) CPM2018-94 ICD2018-55 IE2018-73
Performance of hybrid storage with storage class memory (SCM) and NAND flash memory is improved by using SCM as non-vola... [more] CPM2018-94 ICD2018-55 IE2018-73
pp.29-30
ICD 2018-04-19
10:10
Tokyo   Reliability Enhancement Technique with Horizontal Error Detection and Vertical-LDPC in 3D-TLC NAND Flash Memories
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi (Chuo Univ.) ICD2018-1
Conventional Asymmetric Coding (AC) has been proposed for improving NAND flash memories. In this work, Horizontal Error ... [more] ICD2018-1
pp.1-6
ICD 2018-04-19
10:35
Tokyo   Application-optimized heterogeneously-integrated storage with non-volatile memories
Chihiro Matsui, Ken Takeuchi (Chuo Univ.) ICD2018-2
Data center storages require application-optimized heterogeneous integration of non-volatile memories. Two types of stor... [more] ICD2018-2
pp.7-10
ICD 2018-04-19
11:00
Tokyo   [Invited Talk] Data-aware Computing with Highly Reliable SSD System
Ken Takeuchi (Chuo Univ.) ICD2018-3
 [more] ICD2018-3
p.11
SDM 2018-01-30
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Lateral Charge Migration Suppression Technique of 3D-NAND Flash by Vth Nearing
Kyoji Mizoguchi, Shohei Kotaki, Yoshiaki Deguchi, Ken Takeuchi (Chuo Univ.) SDM2017-93
In the near data computing, a SSD controller embeds more processing units and RAMs to execute a part of application whic... [more] SDM2017-93
pp.9-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
13:50
Kumamoto Kumamoto-Kenminkouryukan Parea Low Voltage Operation Boost Converter for ReRAM/NAND Flash Memory Hybrid SSD
Kenta Suzuki, Kota Tsurumi, Ken Takeuchi (Chuo Univ.) CPM2017-82 ICD2017-41 IE2017-67
 [more] CPM2017-82 ICD2017-41 IE2017-67
pp.15-20
ICD 2017-04-20
13:50
Tokyo   [Invited Lecture] A 1.0 V Operation NAND Flash Memory Program Voltage Generator Fabricated with Standard CMOS Process and NAND Flash Process for IoT Local Devices
Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi (Chuo Univ.) ICD2017-5
NAND flash memory is considered as candidates for data storage of IoT local devices. The NAND flash memory program volta... [more] ICD2017-5
pp.23-28
ICD 2017-04-20
14:15
Tokyo   [Invited Lecture] TLC NAND Flash Memory Control Techniques to Reduce Errors of Read-Hot and Cold Data for Data Centers
Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2017-6
In cloud data centers, NAND flash memory stores both read-hot and cold data. This paper describes that the threshold vol... [more] ICD2017-6
pp.29-34
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology [Poster Presentation] Optimal Program Conditions of ReRAM
Atsuna Hayakawa, Kazuki Maeda, Ken Takeuchi (Chuo Univ.) ICD2016-65 CPSY2016-71
 [more] ICD2016-65 CPSY2016-71
p.49
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology [Poster Presentation] Analysis of Read Disturb Error in NAND Flash Memory
Hikaru Watanabe, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2016-66 CPSY2016-72
Recently, as cloud computing technology and Social Networking Service spread, the applications whose data is read locall... [more] ICD2016-66 CPSY2016-72
p.51
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology [Poster Presentation] High-Speed Operation of Program Voltage Generator for Low-voltage ReRAM
Kenta Suzuki, Masahiro Tanaka, Kota Tsurumi, Ken Takeuchi (Chuo Univ.) ICD2016-67 CPSY2016-73
Resistive random access memory (ReRAM) is considered as one of the next generation non-volatile memories due to its high... [more] ICD2016-67 CPSY2016-73
p.53
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology [Poster Presentation] Performance Evaluation of Storage Class Memory based SSD in Consideration of Reliability
Yutaka Adachi, Hirofumi Takishita, Ken Takeuchi (Chuo Univ.) ICD2016-68 CPSY2016-74
The future Storage Class Memory (SCM) is equivalent to NAND Flash in terms of cost. SCM is high performance compared wit... [more] ICD2016-68 CPSY2016-74
p.55
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology [Poster Presentation] Error Pattern Analysis among Scaled Generations of NAND Flash Memories
Yukiya Sakaki, Yusuke Yamaga, Ken Takeuchi (Chuo Univ.) ICD2016-69 CPSY2016-75
The capacity of NAND flash memory can be expanded by memory cell scaling. However, bit-errors are increased by memory ce... [more] ICD2016-69 CPSY2016-75
p.57
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