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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, IPSJ-ARC 2008-05-14
14:15
Tokyo   Performance Balancing: An Efficient Helper-Thread Execution on CMPs
Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
Conventional CMPs attempt to exploit the thread-level parallelism (TLP)
by using all of the cores integrated in a chip.... [more]
ICD2008-31
pp.75-80
ICD, IPSJ-ARC 2008-05-14
17:00
Tokyo   Performance Balancing: An Implementation of Efficient On-chip Memory Hierarchy on Cell/B.E.
Tetsuo Hayashi, Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
We have proposed the concept of Performance Balancing to improve the CMP performance. This approach attempts to exploit ... [more] ICD2008-36
pp.105-110
 Results 1 - 2 of 2  /   
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