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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 13:45 |
Hiroshima |
Satellite Campus Hiroshima (Hiroshima) |
A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2018-69 DC2018-55 |
[more] |
VLD2018-69 DC2018-55 pp.203-208 |
SDM, ICD, ITE-IST [detail] |
2018-08-07 11:30 |
Hokkaido |
Hokkaido Univ., Graduate School of IST M Bldg., M151 (Hokkaido) |
Comparison of Sensitivity to Soft Errors of NMOS and PMOS Transistors by Using Three Types of Stacking Latches in an FDSOI process Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) SDM2018-28 ICD2018-15 |
(To be available after the conference date) [more] |
SDM2018-28 ICD2018-15 pp.15-20 |
VLD, HWS (Joint) |
2018-02-28 17:20 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103 |
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] |
VLD2017-103 pp.85-90 |
VLD, HWS (Joint) |
2018-02-28 17:45 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104 |
Moore's Law has been miniaturizing integrated circuits, which
can make a lot of high performance devices such as PCs an... [more] |
VLD2017-104 pp.91-96 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus (Osaka) |
Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43 |
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more] |
VLD2016-49 DC2016-43 pp.31-36 |
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