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All Technical Committee Conferences (Searched in: Recent 10 Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, VLD [detail] |
2020-03-07 13:00 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) (Cancelled but technical report was issued) |
An Inductive Impulse Self-Destructor in Sense-and-React Countermeasure Against Physical Attacks Sho Tada, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Kazuo Sakiyama (UEC), Noriyuki Miura (Kobe Univ.) VLD2019-141 HWS2019-114 |
[more] |
VLD2019-141 HWS2019-114 pp.275-277 |
HWS, VLD [detail] |
2020-03-07 13:50 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) (Cancelled but technical report was issued) |
Light-Weight Design Methodology of Bulk Current Sensor Against Laser Fault Injection Attack on Cryptographic Processor Yuki Yamashita, Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2019-143 HWS2019-116 |
[more] |
VLD2019-143 HWS2019-116 pp.283-284 |
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] |
2019-07-24 14:10 |
Kochi |
Kochi University of Technology (Kochi) |
Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 |
This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] |
ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 pp.375-382 |
HWS, VLD |
2019-03-02 10:00 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) |
An ultra-light weight implementation of PRINCE-family cryptographic processor Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2018-137 HWS2018-100 |
An ultra-light-weight PRINCE cryptographic processor was proposed by Miura, et al. in 2017.
In this paper, based on thi... [more] |
VLD2018-137 HWS2018-100 pp.261-265 |
HWS |
2018-04-13 15:25 |
Fukuoka |
(Fukuoka) |
A Compact Countermeasure against Laser-Fault-Injection Attack Utilizing Bulk-Current Sensor and Instantaneous Supply-Shunt Circuit Kohei Matsuda (Kobe Univ.), Tatsuya Fujii, Shoji Natsu, Takeshi Sugawara, Kazuo Sakiyama (UCE), Yu-ichi Hayashi (NAIST), Makoto Nagata, Noriyuki Miura (Kobe Univ.) HWS2018-8 |
A compact sense-and-reacts countermeasure is proposed against laser fault injection attack on cryptographic processors. ... [more] |
HWS2018-8 pp.41-44 |
ICD, CPSY, CAS |
2017-12-14 09:30 |
Okinawa |
Art Hotel Ishigakijima (Okinawa) |
Chip-Package-Board Interactive PUF Based on Chaos Oscillation Masanori Takahashi, Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) CAS2017-63 ICD2017-51 CPSY2017-60 |
This paper presents a new concept of PUF based on a chaotic behavior. Chaos is essentially not a random phenomenon but a... [more] |
CAS2017-63 ICD2017-51 CPSY2017-60 pp.1-2 |
HWS (2nd) |
2017-06-12 16:50 |
Aomori |
Hirosaki University (Aomori) |
Ultra-Light-Weight Implementation of PRINCE Cryptographic Processor Kohei Matsuda, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Shivam Bashin (Nanyang Tech. Univ.), Ville Yli-Mayry, Naofumi Homma (Tohoku Univ.), Yves Mathieu, Tarik Graba, Jean-Luc Danger (Telecom ParisTech) |
(Advance abstract in Japanese is available) [more] |
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