IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 31  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-29
09:40
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
Test Generation Merhod based on RTL Design for Diagnosability
Yuya Chida, Toshinori Hosokawa (Nihon univ.), Koji Yamazaki (Meiji Univ.) VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49
 [more] VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49
pp.43-48
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:50
Online Online A Test Generatoin Method to Improve Diagonostic Resolution Based on Fault Sensitization Coverage
Yuya Chida, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) CPSY2021-57 DC2021-91
As one of test generation methods to achieve high defect coverage, n-detection test generation methods have been propose... [more] CPSY2021-57 DC2021-91
pp.73-78
DC 2022-03-01
15:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
Evaluation of Don't Care Filling Method of Control Signals to Enhance Fault Diagnosability for Logic and Timing Fault
Kohei Tsuchibuchi, Xu Haofeng, Yuya Chida, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ) DC2021-76
 [more] DC2021-76
pp.69-74
DC 2022-03-01
16:10
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.) DC2021-77
 [more] DC2021-77
pp.75-80
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:00
Online Online An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.) CPSY2020-61 DC2020-91
Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis... [more] CPSY2020-61 DC2020-91
pp.67-72
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:20
Online Online A Don't Care Filling Method of Control Signals for Controllers to Enhance Fault Diagnosability at Register Transfer Level
Kohei Tsuchibuchi, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ.) CPSY2020-62 DC2020-92
With the progress of semiconductor technology in recent years, fault analysis is important to improve the yield of VLSIs... [more] CPSY2020-62 DC2020-92
pp.73-78
HWS, VLD 2019-02-27
17:10
Okinawa Okinawa Ken Seinen Kaikan Improvement on DMA Transfer Efficiency by Packet Concatenation
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) VLD2018-106 HWS2018-69
(To be available after the conference date) [more] VLD2018-106 HWS2018-69
pp.79-84
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
11:20
Hiroshima Satellite Campus Hiroshima An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura (NTT), Koji Yamazaki (NTT-AT), Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) VLD2018-55 DC2018-41
(To be available after the conference date) [more] VLD2018-55 DC2018-41
pp.113-118
NS, IN
(Joint)
2018-03-01
11:30
Miyazaki Phoenix Seagaia Resort A study of feasibility evaluation for performance estimation on network hardware abstraction
Yuki Takei, Satoshi Nishiyama, Saki Hatta, Koji Yamazaki (NTT) NS2017-186
When deploying the network functions at optimal positions by using the hardware devices such as CPU, FPGA and NPU, it is... [more] NS2017-186
pp.109-112
DC 2016-02-17
14:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis
Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Koji Yamazaki (Meiji Univ.) DC2015-91
 [more] DC2015-91
pp.31-36
NS, IN
(Joint)
2015-03-03
14:30
Okinawa Okinawa Convention Center Hierarchically Structured Spatio-Temporal Traffic Measurement utilizing Compressive Sensing
Yoshihiro Tsuji, Yuichi Ohsita, Masayuki Murata (Osaka Univ.), Koji Yamazaki, Akihiko Miyazaki (NTT) IN2014-162
 [more] IN2014-162
pp.243-248
DC 2015-02-13
16:00
Tokyo Kikai-Shinko-Kaikan Bldg An Evalution of a Fault Diagnosis Method for Single Logical Faults Using Multi Cycle Capture Test Sets
Hideyuki Takano, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) DC2014-86
Multi-cycle capture testing has been proposed to improve test quality of scan testing. However, fault diagnosis for mult... [more] DC2014-86
pp.49-54
DC 2014-02-10
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation
Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] DC2013-89
pp.61-66
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
14:35
Kagoshima   A Study on the Design of Processor System for Stream Processing
Yusuke Sekihara, Koji Yamazaki, Akihiko Miyazaki (NTT) VLD2013-101 DC2013-67
Processing performance required for packet data transfer system has been improving year by year due to the high-speed da... [more] VLD2013-101 DC2013-67
pp.287-292
VLD, IPSJ-SLDM 2013-05-16
09:50
Fukuoka Kitakyushu International Conference Center A Longest Path Algorithm for Differential Pair Net Considering Connectivity
Koji Yamazaki, Yukihide Kohira (Univ. of Aizu) VLD2013-3
In recent years, due to the speedup and miniaturization in LSI systems, PCB routing design uses many differential pair n... [more] VLD2013-3
pp.13-18
DC 2013-02-13
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. Characteristic Analysis of Signal Delay for Resistive Open Fault Detection
Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] DC2012-84
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
16:25
Fukuoka Centennial Hall Kyushu University School of Medicine A Study on Test Generation for Effective Test Compaction
Yukino Kusuyama, Tatuya Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) VLD2012-105 DC2012-71
In recent year, the numbers of target fault models and faults for testing increase because the number of gates on VLSIs ... [more] VLD2012-105 DC2012-71
pp.267-272
DC 2012-06-22
14:20
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg [Invited Talk] Empirical study for signal integrity-defects
Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. Tokushima) DC2012-12
We try to empirically study signal integrity-defects.
In this study, we analyze the resistive open fault that causes th... [more]
DC2012-12
pp.21-26
DC 2010-02-15
10:00
Tokyo Kikai-Shinko-Kaikan Bldg. Study on a Test Generation Method for Transition Faults Using Multi Cycle Capture Test
Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2009-67
Overtesting induces unnecessary yield loss. Untestable faults have no effect on normal functions of circuits. However, i... [more] DC2009-67
pp.13-18
DC 2010-02-15
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Modeling resistive open faults and generating their tests
Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2009-68
In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive ope... [more] DC2009-68
pp.19-24
 Results 1 - 20 of 31  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan