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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
IN, NS
(Joint)		 2021-03-04
09:30		 Online Online A Study on Availability Enhancement for State Transition based Networked Control System
Koki Igawa, Yohei Tsukamoto, Osamu Toyama, Katsuyoshi Takahashi (Mitsubishi Electric) NS2020-128		 In recent years, a control system, where input/output nodes and a controller node with control logic are connected to ne... [more] NS2020-128
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]		 2016-11-30
13:20		 Osaka Ritsumeikan University, Osaka Ibaraki Campus An aging aware high-level synthesis algorithm with floorplanning
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-68 DC2016-62		 (To be available after the conference date) [more] VLD2016-68 DC2016-62
pp.141-146
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
13:25		 Kanagawa Hiyoshi Campus, Keio University A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87		 Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] VLD2015-105 CPSY2015-137 RECONF2015-87
pp.209-214
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
15:10		 Oita B-ConPlaza A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures
Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40		 In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] VLD2014-86 DC2014-40
pp.105-110
 Results 1 - 4 of 4  /   
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