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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
13:25
Kanagawa   A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84
Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] VLD2012-130 CPSY2012-79 RECONF2012-84
pp.135-140
RECONF 2011-09-26
15:30
Aichi Nagoya Univ. Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers
Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29
Preemption techniques for HW (hardware) tasks
have been studied in order to improve their responsiveness
and to allow ... [more]
RECONF2011-29
pp.43-48
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
10:25
Kanagawa Keio Univ (Hiyoshi Campus) Effective Hardware Task Context Switching in Virtex-4 FPGAs
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2009-87 CPSY2009-69 RECONF2009-72
A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic... [more] VLD2009-87 CPSY2009-69 RECONF2009-72
pp.113-118
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