IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 2 of 2  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, VLD 2006-03-10
15:35
Okinawa   An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design
Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)
In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltag... [more] VLD2005-132 ICD2005-249
pp.61-66
SIP, ICD, IE, IPSJ-SLDM 2005-10-20
16:30
Miyagi Ichinobo, Sakunami-Spa A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] SIP2005-113 ICD2005-132 IE2005-77
pp.107-112
 Results 1 - 2 of 2  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan