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 Results 1 - 20 of 27  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2018-08-08
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 [Invited Lecture] A Highly Symmetrical 10T 2-Read/Write Dual-port SRAM Bitcell Design In 28nm High-k/Metal-gate Planar Bulk CMOS Technology
Yuichiro Ishii, Miki Tanaka, Makoto Yabuuchi, Yohei Sawada, Shinji Tanaka, Koji Nii (Renesas), Tien Yu Lu, Chun Hsien Huang, Shou Sian Chen, Yu Tse Kuo, Ching Cheng Lung, Osbert Cheng (UMC) SDM2018-40 ICD2018-27
We propose a highly symmetrical 10T 2-read/write (2RW) dual-port (DP) SRAM bitcell in 28-nm high-k/metal-gate planar bul... [more] SDM2018-40 ICD2018-27
SDM, ICD, ITE-IST [detail] 2018-08-09
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 12-nm Fin-FET 3.0G-search/s 80-bit x 128-entry Dual-port Ternary CAM
Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka (Renesas) SDM2018-48 ICD2018-35
 [more] SDM2018-48 ICD2018-35
ICD 2018-04-20
Tokyo   [Invited Lecture] An Implementation of 2RW Dual-Port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT
Yohei Sawada, Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Makoto Yabuuchi (REL), Yoshihiro Shinozaki, Kyoji Ito (NSW), Shinji Tanaka, Nii Koji, Shiro Kamohara (REL) ICD2018-8
 [more] ICD2018-8
SDM, ICD, ITE-IST [detail] 2017-07-31
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. A 65 nm 1.0V 1.84ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT
Makoto Yabuuchi, Koji Nii, Shinji Tanaka (Renesas), Shinozaki Yoshihiro (Nippon Systemware), Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Shiro Kamohara (Renesas) SDM2017-33 ICD2017-21
 [more] SDM2017-33 ICD2017-21
ICD 2017-04-21
Tokyo   [Invited Lecture] A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time
Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL) ICD2017-12
 [more] ICD2017-12
(Joint) [detail]
Hiroshima Miyajima-Morino-Yado(Hiroshima) A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
SDM 2016-01-28
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes
Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125
 [more] SDM2015-125
ICD 2015-04-16
Nagano   [Invited Lecture] 20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists
Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii (Renesas) ICD2015-1
 [more] ICD2015-1
ICD 2015-04-16
Nagano   [Invited Lecture] A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline
Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2
 [more] ICD2015-2
SDM 2015-01-27
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM Macros with Wordline Overdriven Assist
Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Miki Tanaka, Koji Nii (Renesas) SDM2014-144
We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Tes... [more] SDM2014-144
ICD 2014-01-28
Kyoto Kyoto Univ. Tokeidai Kinenkan [Poster Presentation] An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory
Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST) ICD2013-125
Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] ICD2013-125
SDM, ICD 2013-08-02
Ishikawa Kanazawa University A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58
 [more] SDM2013-76 ICD2013-58
SDM, ICD 2013-08-02
Ishikawa Kanazawa University 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] SDM2013-77 ICD2013-59
ICD 2012-12-18
Tokyo Tokyo Tech Front A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM
Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii (Renesas) ICD2012-114
 [more] ICD2012-114
ICD 2012-04-24
Iwate Seion-so, Tsunagi Hot Spring (Iwate) [Invited Talk] Write-/Read- Disturb Issues and Circuit Solutions
Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] ICD2012-11
ICD 2012-04-24
Iwate Seion-so, Tsunagi Hot Spring (Iwate) A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST
Hidehiro Fujiwara, Makoto Yabuuchi, Hirofumi Nakano, Hiroyuki Kawai, Koji Nii, Kazutami Arimoto (Renesas Electronics) ICD2012-17
 [more] ICD2012-17
SDM, ICD 2011-08-26
Toyama Toyama kenminkaikan Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas) SDM2011-91 ICD2011-59
 [more] SDM2011-91 ICD2011-59
SDM, ICD 2011-08-26
Toyama Toyama kenminkaikan A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas) SDM2011-93 ICD2011-61
In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design ... [more] SDM2011-93 ICD2011-61
ICD 2010-04-22
Kanagawa Shonan Institute of Tech. [Invited Talk] Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies -- A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias --
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara (Renesas Electronics) ICD2010-2
We investigate 0.5V 6T-SRAM with asymmetric MOSFET, which contributes to enhance the read and write margin. We also intr... [more] ICD2010-2
ICD 2010-04-22
Kanagawa Shonan Institute of Tech. A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] ICD2010-3
 Results 1 - 20 of 27  /  [Next]  
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