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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2011-02-07
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. Path-finding for Integration of Robust Low-k (k-2.5) SiOCH in System LSI
Naoya Inoue, Makoto Ueki, Hironori Yamamoto, Ippei Kume, Jun Kawahara, Manabu Iguchi, Hirokazu Honda, Yoshitaka Horikoshi, Yoshihiro Hayashi (Renesas Electronics Corp.) SDM2010-217
Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-val... [more] SDM2010-217
pp.7-12
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