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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 31  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2023-03-24
14:30
Kagoshima Amagi Town Disaster Prevention Center (Tokunoshima)
(Primary: On-site, Secondary: Online)
A study of reinforcemtent learning-based AGV route scheduling using local graph information
Hirotada Sugimoto, Shaswot Shresthamali, Masaaki Kondo (Keio Univ.) CPSY2022-49 DC2022-108
In this paper, we propose a reinforcement learning-based route planning method for multiple AGVs. The proposed scheduli... [more] CPSY2022-49 DC2022-108
pp.89-94
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
14:30
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Anomaly Detection using On-Device Learning Algorithm on Wireless Sensor Nodes
Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani (Keio Univ.) CPSY2022-10 DC2022-10
 [more] CPSY2022-10 DC2022-10
pp.53-58
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-11
14:50
Online Online A Study on an Acceleration of Graph-Based SLAM with FPGA
Hajime Takishita, Yuan He, Masaaki Kondo, Hideharu Amano (Keio Univ.n) CPSY2021-62 DC2021-96
(To be available after the conference date) [more] CPSY2021-62 DC2021-96
pp.103-108
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
15:45
Ehime Ehime Prefecture Gender Equality Center
Ryohei Tomura, Takuya Kojima, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Masaaki Kondo (UTokyo) CPSY2019-49
SNACC (Scalable Neuro Accelerator Core with Cubic integration) is an accelerator for deep neural network, which can impr... [more] CPSY2019-49
pp.65-70
CPSY, DC, IPSJ-ARC [detail] 2019-07-24
10:45
Hokkaido Kitami Civic Hall CPSY2019-17 DC2019-17 (To be available after the conference date) [more] CPSY2019-17 DC2019-17
pp.1-6
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-18
10:35
Kagoshima Nishinoomote City Hall (Tanega-shima) A Method for Improving Accuracy using Multiple Online Unsupervised Anomaly Detection Cores
Mineto Tsukada (Keio Univ.), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.) CPSY2018-114 DC2018-96
 [more] CPSY2018-114 DC2018-96
pp.247-252
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-31
11:00
Kanagawa Raiosha, Hiyoshi Campus, Keio University A Case for Unsupervised Abnormal Behavior Detection Using Multiple Online Sequential Learning Cores
Rei Ito, Mineto Tsukada (Keio Univ), Masaaki Kondo (Univ Tokyo), Hiroki Matsutani (Keio Univ) VLD2018-85 CPSY2018-95 RECONF2018-59
(To be available after the conference date) [more] VLD2018-85 CPSY2018-95 RECONF2018-59
pp.77-82
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2018-08-01
17:30
Kumamoto Kumamoto City International Center A Stable and Efficient Learning Method for FPGA-Based Online Sequential Unsupervised Anomaly Detector
Mineto Tsukada (Keio Univ.), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.) CPSY2018-30
(To be available after the conference date) [more] CPSY2018-30
pp.217-222
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2017-03-10
14:30
Okinawa Kumejima Island Compiler Toolchain of Deep Learning Accelerator with Wireless 3D Stacked Chips
Tetsui Ohkubo, Takuya Kojima, Hideharu Amano (Keio Univ.), Ryo Takata, Jun Ishii, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura (Tokyo Univ.) CPSY2016-155 DC2016-101
 [more] CPSY2016-155 DC2016-101
pp.357-362
ICD, MW 2016-03-02
14:55
Hiroshima Hiroshima University [Invited Talk] An implementation of a building block system with TCI (Thru-Chip Interface) using SOTB process
Hideharu Amano (Keio Univ.), Masayoshi Usami (SIT), Tadahiro Kuroda (Keio Univ.), Masaaki Kondo (Univ. of Tokyo), Yasuhiro Take (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Mitaro Namiki (TUAT), Hiroki Matsutani (Keio Univ.) MW2015-182 ICD2015-105
 [more] MW2015-182 ICD2015-105
pp.49-54
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-07
09:20
Kagoshima   A Study on a Power Efficient Neurochip with Non-Volatile Memory
Jun Tomii, Masaaki Kondo, Hiroshi Nakamura (Univ. Tokyo) CPSY2014-176 DC2014-102
Along with the evolution of machine learning techniques, neurochips, which are designed for fast neural network processi... [more] CPSY2014-176 DC2014-102
pp.83-88
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
17:30
Kanagawa Hiyoshi Campus, Keio University A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) VLD2014-152 CPSY2014-161 RECONF2014-85
The inductive-coupling 3D chip stacking technique has several advantages over TSV-based 3D stacking. For example, its ma... [more] VLD2014-152 CPSY2014-161 RECONF2014-85
pp.245-250
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-16
10:15
Okinawa   A Preliminary Study on Energy Saving of Personal ICT Equipment by User Recognition
Thang Cao, Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) CPSY2013-110 DC2013-97
 [more] CPSY2013-110 DC2013-97
pp.247-252
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
10:25
Kagoshima   Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46
 [more] VLD2013-80 DC2013-46
pp.135-140
CPSY 2013-10-03
11:35
Chiba Makuhari Messe A Chip Evaluation of Cube-1: A multi-core processor with 3D TCI
Hideharu Amano, Yusuke Koizumi (Keio Univ.), Noriyuki Miura (Kobe Univ.), Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Agri. and Tech.), Kimiyoshi Usami, Masaaki Kondo (Univ. of Elect. Comm.), Hiroshi Nakamura (Univ. of Tokyo) CPSY2013-33
 [more] CPSY2013-33
pp.13-18
RECONF 2011-09-26
10:45
Aichi Nagoya Univ. Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1.
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications) RECONF2011-22
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] RECONF2011-22
pp.1-6
DC, CPSY
(Joint)
2011-07-29
13:55
Kagoshima   An Availability Evaluation of GPU Programming Framework to Provide Embedded MPI
Keigo Shima, Takefumi Miyoshi, Masaaki Kondo, Hidetsugu Irie, Hiroki Honda, Tsutomu Yoshinaga (UEC) CPSY2011-17
We proposed a programming framework which enables
programmers to use MPI functions within GPU kernels.
The framework a... [more]
CPSY2011-17
pp.49-54
RECONF 2011-05-13
10:45
Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) Optimization of Application Programs of SLD-1 : A Low Power Accelarator
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] RECONF2011-15
pp.85-90
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
14:50
Kanagawa Keio Univ (Hiyoshi Campus) Silent Large Datapath : A Ultra Low Power Accelarater
Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded
systems. By using a... [more]
VLD2010-109 CPSY2010-64 RECONF2010-78
pp.169-174
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
15:10
Kanagawa Keio Univ (Hiyoshi Campus) Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] VLD2010-110 CPSY2010-65 RECONF2010-79
pp.175-180
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