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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2009-06-19 16:00 |
Tokyo | An401・402 Inst. Indus. Sci., The Univ. of Tokyo | Floating Gate Memory with Biomineralized Nanodots Embedded in High-k Gate Dielectric Kosuke Ohara, Ichiro Yamashita (NAIST), Toshitake Yaegashi, Masahiro Moniwa, Masaki Yoshimaru (STARC), Yukiharu Uraoka (NAIST/CREST)  SDM2009-40 |
The memory properties of nano-dot-type floating gate memories with Co bio-nanodots (Co-BNDs) embedded in HfO2 layer were... [more] | SDM2009-40 pp.77-80 |
| SDM | 2008-06-10 14:35 |
Tokyo | An401・402, Inst. Indus. Sci., The Univ. of Tokyo | Bio-nano dot floating gate memory with High-k films Kosuke Ohara, Yukiharu Uraoka, Takashi Fuyuki, Ichiro Yamashita (NAIST), Toshitake Yaegashi, Masahiro Moniwa, Masaki Yoshimaru (STARC) SDM2008-57 |
The memory characteristics of nanodot floating gate memories with High-k tunnel oxide were investigated using MOS capaci... [more] | SDM2008-57 pp.89-92 |
| SDM, VLD | 2007-10-30 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Electro-Thermal Compact Model for Reset Operation of Phase Change Memories Atsushi Sakai, Kenichiro Sonoda, Masahiro Moniwa, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.) VLD2007-55 SDM2007-199 |
A three-dimensional (3D) electro-thermal compact model for the reset operation of a phase change memory (PCM) cell is pr... [more] | VLD2007-55 SDM2007-199 pp.23-26 |
| ICD | 2007-04-12 11:10 |
Oita | [Invited Talk]
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5 |
An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit... [more] | ICD2007-5 pp.23-28 |
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| SDM | 2007-03-15 13:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories Yuichi Matsui, Kenzo Kurotsuchi, Osamu Tonomura, Takahiro Morikawa, Masaharu Kinoshita, Yoshihisa Fujisaki, Nozomu Matsuzaki, Satoru Hanzawa, Motoyasu Terao, Norikatsu Takaura, Hiroshi Moriya, Tomio Iwasaki (Hitachi), Masahiro Moniwa, Tsuyoshi Koga (Renesas) |
A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., c... [more] | SDM2006-254 pp.1-6 |
| ICD, ITE-CE | 2006-01-26 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas) |
This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, u... [more] | ICD2005-206 pp.7-12 |
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