Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
QIT (2nd) |
2016-11-24 13:00 |
Ibaraki |
KEK Kobayashi-hall |
[Poster Presentation]
FPGA-based Simulation of Quantum Walks on Regular Graphs Daiki Chubachi, Masaki Nakanishi (Yamagata Univ.) |
quantum computer simulator,quantum walk,FPGA [more] |
|
QIT (2nd) |
2013-11-18 12:00 |
Tokyo |
Waseda Univ. |
Quantum Pushdown Automata with a Garbage Space Masaki Nakanishi (Yamagata Univ.) |
Several kinds of quantum pushdown automata have been proposed, and their computational power is investigated
intensivel... [more] |
|
QIT (2nd) |
2013-11-18 - 2013-11-19 |
Tokyo |
Waseda Univ. |
[Poster Presentation]
A Hardware Quantum Circuit Simulator Architecture based on Register Reordering Miki Matsuyama, Yumi Yokoo, Masaki Nakanishi (Yamagata Univ.) |
Quantum circuit simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regard... [more] |
|
KBSE |
2009-09-15 14:00 |
Overseas |
Hanoi University of Technology, Hanoi, Vietnam |
Data-Mining Approach to Road Maintenance Support System Kunitsugu Ichinose (Doshisha Univ.), Masaki Nakanishi, Morimasa Terada (Kyoto Pref.), Yuki Fujisawa, Shigeo Kaneda (Doshisha Univ.) KBSE2009-26 |
[more] |
KBSE2009-26 pp.51-56 |
CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi |
|
An efficient middle-level framework for quantum circuit simulation on multiple simulator platforms Antti Vikman, Takashi Nakada (NAIST), Masaki Nakanishi (Yamagata Univ.), Shigeru Yamashita (Ritsumeikan Univ.), Yasuhiko Nakashima (NAIST) CPSY2009-14 |
Simulating of quantum computers is hard task for any classical computer. Even though multiple simulation libraries have ... [more] |
CPSY2009-14 pp.25-30 |
ICD, IPSJ-ARC, IPSJ-EMB |
2009-01-14 13:15 |
Osaka |
Shoushin Kaikan |
Feasibility of an Embedded Virtual Machine under Parallel or Distributed Processing Environment Hirofumi Yano, Masaki Nakanishi, Shinobu Miwa, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) |
[more] |
ICD2008-142 pp.75-80 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 16:30 |
Fukuoka |
Kitakyushu Science and Research Park |
Evaluating the reliability of Highly Reliable Cell Circuits Keiichi Hotta, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) VLD2008-75 DC2008-43 |
Recently, the shrinking process causes transistor variation and growth of error rate. Highly Reliable Cells (HRCs) have ... [more] |
VLD2008-75 DC2008-43 pp.91-96 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 16:15 |
Fukuoka |
Kitakyushu Science and Research Park |
Soft Error Mitigation Techniques for FPGA Switch Matrices Yuki Kou, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) RECONF2008-45 |
Recentry, a soft error becomes a serious probrem as the process shrinking. Especially, SRAMs seriously suffer from a sof... [more] |
RECONF2008-45 pp.39-44 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2008-03-28 13:50 |
Kagoshima |
|
A Functional Unit with Small Variety of Highly Reliable Cells and Its Evaluation Kazunori Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST) DC2007-112 CPSY2007-108 |
Recently, the shrinking process causes growth of error rate. We have proposed new standard cells in which transistors ar... [more] |
DC2007-112 CPSY2007-108 pp.167-172 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 09:00 |
Fukuoka |
Kitakyushu International Conference Center |
Designing Soft Error Tolerant LUTs of SRAM-based FPGAs Kohei Satoyama, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST) RECONF2007-43 |
Recently, soft error becomes a serious problem as the process shrinks. Especially, SRAMs seriously suffer from soft erro... [more] |
RECONF2007-43 pp.1-6 |
VLD, IPSJ-SLDM |
2006-05-11 14:00 |
Ehime |
Ehime University |
Online FPGA Placement Using I/O Routing Information Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita (NAIST), Kazuo Nakajima (Univ. of Maryland), Katsumasa Watanabe (NAIST) |
[more] |
VLD2006-1 pp.1-6 |
SS |
2006-02-02 16:15 |
Fukuoka |
Fukuoka Laboratory for Emerging and Enabling Technology of SoC |
create the framework of active program from pi-expression Katsumasa Watanabe (NAIST), LO Fuchuan (TOPPAN CFI), Masaki Nakanishi, Shigeru Yamashita (NAIST) |
The active program with active functions has soft form
and is suitable to safe execution and modification.
The active ... [more] |
SS2005-81 pp.29-34 |
RECONF |
2005-12-02 09:55 |
Fukuoka |
Kitakyushu International Conference Center |
Online FPGA Placement under I/O Timing Constraints Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
In recent years, FPGAs are effectively-utilized in various fields.
Among them, devices with partial reconfiguration are... [more] |
RECONF2005-73 pp.7-12 |
ISEC, IPSJ-CSEC, SITE |
2005-07-22 13:25 |
Iwate |
Iwate Prefectural University |
Cheater Identifiable Quantum Secret Sharing Schemes Yumiko Murakami (NAIST/JST-ERATO), Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
In this paper, we show that there exists a cheater identifiable
$(k, n)$ threshold secret sharing scheme for a quantum ... [more] |
ISEC2005-55 pp.89-92 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 10:00 |
Kanagawa |
|
Reconfigurable 1-bit processor array with reduced wiring area Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement a... [more] |
VLD2004-98 CPSY2004-64 pp.7-12 |
SS |
2004-11-26 09:30 |
Yamanashi |
Univ. of Yamanashi, Kofu(Takeda) Campus |
Support Mechanism of Software Self-regulation Katsumasa Watanabe, Akihiro Inoue, Youhei Yamada, Masaki Nakanishi, Shigeru Yamashita (NAIST) |
The concept of active software is proposed as a basis of software design methodology, which is suitable to the uncertain... [more] |
SS2004-34 pp.1-6 |
ISEC, IPSJ-CSEC |
2004-07-20 15:50 |
Tokushima |
Tokushima Univ. |
Certification of Program Execution by Tamper Resistant CPU Atsuya Okazaki, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
In grid computing and mobile agents system, remote computers may be untrusted. It is difficult to certify that remote co... [more] |
ISEC2004-37 pp.165-170 |