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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IPSJ-ARC | 2008-05-14 09:30 |
Tokyo | Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas)  ICD2008-26 |
A multicore SoC has been developed for various applications (recognition, inference, measurement, control and security) ... [more] | ICD2008-26 pp.45-50 |
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| ICD, ITE-CE | 2007-12-14 14:40 |
Kochi | A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] | ICD2007-138 pp.107-111 |
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| CPSY | 2007-10-25 13:00 |
Kumamoto | Kumamoto University | The application of the massively parallel processor based on the matrix architecture Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24 |
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] | CPSY2007-24 pp.1-5 |
| ICD, SDM | 2007-08-23 08:30 |
Hokkaido | Kitami Institute of Technology | Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Hayato Fujiwara, Kazuya Ishida, Naoto Okumura, Norio Masui, Hiroyuki Kondo (Renesas) SDM2007-141 ICD2007-69 |
A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The co... [more] | SDM2007-141 ICD2007-69 pp.1-4 |
| ICD, SDM | 2006-08-17 09:05 |
Hokkaido | Hokkaido University | A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture Tetsushi Tanizaki, Takayuki Gyohten, Hideyuki Noda, Masami Nakajima, Katsuya Mizumoto, Katsumi Dosaka (Renesas) |
A super parallel SIMD processor based on the matrix architecture which consists of 2k processors, embedded SRAM, and tim... [more] | SDM2006-125 ICD2006-79 pp.1-6 |
| ICD | 2006-05-25 13:00 |
Hyogo | Kobe University | A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips -- Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) |
We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] | ICD2006-25 pp.19-23 |
| RECONF | 2005-05-13 13:00 |
Kyoto | Kyoto University | [Invited Talk]
Programmable Device Technologies for SoC Embedded Applications Masami Nakajima, Hideyuki Noda, Kazutami Arimoto (Renesas) |
SoC for digital consumer market requires short time and low cost of development and easy system change. SoC development ... [more] | RECONF2005-21 pp.37-42 |
| RECONF | 2005-05-13 14:00 |
Kyoto | Kyoto University | A performance evaluation of SIMD type accelerator for JPEG2000 application Fumiaki Senoue, Kozo Komoda, Masahiro Iida, Morihiro Kuga (Kumamoto Univ.), Hideyuki Noda, Masami Nakajima (Renesas), Toshinori Sueyoshi (Kumamoto Univ.) |
Embedded processor is often complemented with dedicated hardware or reconfigurable logic in order to execute complicated... [more] | RECONF2005-22 pp.43-48 |
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