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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2018-08-09
13:10
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 12-nm Fin-FET 3.0G-search/s 80-bit x 128-entry Dual-port Ternary CAM
Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka (Renesas) SDM2018-48 ICD2018-35
 [more] SDM2018-48 ICD2018-35
pp.115-120
ICD 2017-04-21
10:25
Tokyo   [Invited Lecture] A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time
Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL) ICD2017-12
 [more] ICD2017-12
pp.63-65
ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT
(Joint) [detail]
2017-01-31
15:25
Hiroshima Miyajima-Morino-Yado(Hiroshima) A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
pp.87-92
SDM 2016-01-28
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes
Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125
 [more] SDM2015-125
pp.21-25
SDM, ICD 2015-08-24
15:50
Kumamoto Kumamoto City Area and Performance Study of FinFET with Detailed Parasitic Capacitance Analysis in 16nm Process Node
Takeshi Okagaki, Koji Shibutani, Masao Morimoto, Yasumasa Tsukamoto, Koji Nii, Kazunori Onozawa (REL) SDM2015-64 ICD2015-33
 [more] SDM2015-64 ICD2015-33
pp.37-40
ICD 2015-04-16
13:00
Nagano   [Invited Lecture] 20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists
Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii (Renesas) ICD2015-1
 [more] ICD2015-1
pp.1-4
SDM 2015-01-27
15:55
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM Macros with Wordline Overdriven Assist
Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Miki Tanaka, Koji Nii (Renesas) SDM2014-144
We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Tes... [more] SDM2014-144
pp.37-40
ICD 2013-04-12
15:30
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics) ICD2013-21
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has two low-vo... [more] ICD2013-21
pp.109-114
ICD 2010-04-22
11:15
Kanagawa Shonan Institute of Tech. A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation
Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] ICD2010-4
pp.17-21
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-28
11:45
Fukuoka Kitakyushu International Conference Center Asymmetric Slope Differential Logic with High-Speed and Low-Power Operation Modes
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki (AIL)
 [more] VLD2006-60 DC2006-47
pp.53-58
VLD, ICD, DC, IPSJ-SLDM 2005-11-30
16:10
Fukuoka Kitakyushu International Conference Center Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki
This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The te... [more] VLD2005-58 ICD2005-153 DC2005-35
pp.25-30
 Results 1 - 11 of 11  /   
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