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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 77  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-28
15:00
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
A secret key identification method for SFLL-HD to resist the FALL attack
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.)
 [more]
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-29
10:20
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
Seed Generation Method for Multiple Random Resistant Stuck-at Faults in Built-In Self-Test
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)
 [more]
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
10:15
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Faster low-power oriented test generation methods using fault excitation conditions
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) CPSY2022-2 DC2022-2
 [more] CPSY2022-2 DC2022-2
pp.7-12
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
11:00
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults
Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] CPSY2022-3 DC2022-3
pp.13-18
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
11:30
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Field Testability Evaluation Using State Signal Sequences Based on k-Consecutive State Transitions for Field Testing
Yudai Toyooka, Yuki Watanabe, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2022-4 DC2022-4
 [more] CPSY2022-4 DC2022-4
pp.19-24
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:30
Online Online A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing
Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] CPSY2021-56 DC2021-90
pp.67-72
DC 2022-03-01
13:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] DC2021-72
pp.45-50
DC 2022-03-01
15:10
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
State assignment method to improve transition fault coverage for controllers including invalid states
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) DC2021-75
 [more] DC2021-75
pp.63-68
DC 2021-12-10
13:00
Kagawa
(Primary: On-site, Secondary: Online)
A Low Power Oriented Multiple Target Test Generation Method
Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] DC2021-55
pp.1-6
DC 2021-12-10
14:00
Kagawa
(Primary: On-site, Secondary: Online)
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] DC2021-57
pp.13-18
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:40
Online Online A Controller Augmentation method to Improving Transition Fault Coverage
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) CPSY2020-63 DC2020-93
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern VLSIs are increasin... [more] CPSY2020-63 DC2020-93
pp.79-84
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
12:00
Online Online A Logic Locking Method Based on Anti-SAT at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] CPSY2020-64 DC2020-94
pp.85-90
DC 2021-02-05
14:00
Online Online Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] DC2020-74
pp.30-35
DC 2021-02-05
15:30
Online Online A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] DC2020-77
pp.48-53
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
15:45
Online Online A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] CPSY2020-12 DC2020-12
pp.75-80
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
17:30
Online Online An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] CPSY2020-15 DC2020-15
pp.93-98
HWS, VLD [detail] 2020-03-06
14:30
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver
Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] VLD2019-131 HWS2019-104
pp.215-220
DC 2020-02-26
12:00
Tokyo   A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs
Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2019-90
With the complexity for VLSIs, transition fault testing is required. However, VLSIs generally have more untestable trans... [more] DC2019-90
pp.25-30
DC 2020-02-26
14:10
Tokyo   A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT
Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2019-92
Recently, in at-speed scan testing, excessive capture power dissipation is a serious problem. Low capture power test gen... [more] DC2019-92
pp.37-42
DC, SS 2019-10-24
16:00
Kumamoto Kumamoto Univ. A Non-scan Online Test Based on Covering n-Time State Transition
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47
As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] SS2019-19 DC2019-47
pp.37-42
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