Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2025-02-18 10:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
A Heuristic Algorithm of Design for Diagnosability Based on Don't Care Filling of Control Signals Yui Otsuka, Toshinori Hosokawa (Nihon Univ.), Kouji Yamazaki (Meiji Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) |
(To be available after the conference date) [more] |
|
DC |
2025-02-18 15:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
A Status Signal Sequence Generation Method to Improve Optimistically Estimated Field Random Testability Kyosuke Hirose, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
(To be available after the conference date) [more] |
|
DC |
2024-12-06 14:00 |
Oita |
Southern Cross Community Square (Oita) |
A Multiple Target Seed Generation Method for Random Pattern Resistant Faults Using k-Time Expansion Models Takanobu Sone, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) DC2024-98 |
In recent years, with high density of very large-scale integrated circuits (VLSIs), it has become impractical to store a... [more] |
DC2024-98 pp.1-6 |
CPSY, DC, RECONF, IPSJ-ARC [detail] |
2024-08-08 09:50 |
Tokushima |
Awagin Hall (Tokushima, Online) (Primary: On-site, Secondary: Online) |
A Test Pattern Replacement Method to Achieve Both Complete Fault Efficiency and Complete Diagnosis Resolution Tatsuya Aono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Koji Yamazaki (Meiji Univ.) CPSY2024-17 DC2024-17 RECONF2024-17 |
It is important that the test set used for fault diagnosis has high the fault efficiency and is able to distinguish a la... [more] |
CPSY2024-17 DC2024-17 RECONF2024-17 pp.5-10 |
CPSY, DC, RECONF, IPSJ-ARC [detail] |
2024-08-08 16:45 |
Tokushima |
Awagin Hall (Tokushima, Online) (Primary: On-site, Secondary: Online) |
X-Filling and Test Scheduling Methods for Concurrent Testing Using Optimistically/Pessimistically Structural Symbolic Simulation Haruta Tokuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2024-25 DC2024-25 RECONF2024-25 |
In recent years, with the increasing test cost of VLSIs, it has become important to reduce the number of test patterns. ... [more] |
CPSY2024-25 DC2024-25 RECONF2024-25 pp.46-51 |
DC |
2024-02-28 14:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
A Low Power Oriented Multiple Target Test Generation Method for 2 Cycle Gate-Exhaustive Faults Using Pseudo Boolean Optimization Momona Mizota, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyou Uni), Masayuki Arai (Nihon Univ) DC2023-99 |
[more] |
DC2023-99 pp.29-34 |
DC |
2024-02-28 15:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
On Additional Status Signal Sequences Generation to Improve Estimated Field Random Testability for Datapaths at Register Transfer Level Yudai Toyooka, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2023-102 |
[more] |
DC2023-102 pp.47-52 |
DC |
2023-12-08 13:50 |
Nagasaki |
ARKAS SASEBO (Nagasaki, Online) (Primary: On-site, Secondary: Online) |
A Multiple Target Seed Generation Method for Random Pattern Resistant Faults Using a Compatible Fault Set on Built-in Self Test Takanobu Sone, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) DC2023-88 |
In recent years, with high density of very large-scale integrated circuits, it has become impractical to store a large n... [more] |
DC2023-88 pp.7-12 |
CPSY, DC, IPSJ-ARC [detail] |
2023-08-03 10:55 |
Hokkaido |
Hakodate Arena (Hokkaido, Online) (Primary: On-site, Secondary: Online) |
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) CPSY2023-11 DC2023-11 |
[more] |
CPSY2023-11 DC2023-11 pp.19-24 |
CPSY, DC, IPSJ-ARC [detail] |
2023-08-03 11:20 |
Hokkaido |
Hakodate Arena (Hokkaido, Online) (Primary: On-site, Secondary: Online) |
A Don't Care Filling Method of Control Signals in Controllers to Maximize the Number of Distinguishable Weighted Hardware Element Pairs Yui Otsuka, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Koji Yamazaki (Meiji Univ.) CPSY2023-12 DC2023-12 |
[more] |
CPSY2023-12 DC2023-12 pp.25-30 |
HWS, VLD |
2023-03-03 11:50 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-105 HWS2022-76 |
[more] |
VLD2022-105 HWS2022-76 pp.173-178 |
HWS, VLD |
2023-03-03 13:50 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on Function Modification Circuit Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78 |
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] |
VLD2022-107 HWS2022-78 pp.185-190 |
DC |
2023-02-28 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg (Tokyo, Online) (Primary: On-site, Secondary: Online) |
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU) DC2022-89 |
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrat... [more] |
DC2022-89 pp.39-44 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-29 10:05 |
Kumamoto |
(Kumamoto, Online) (Primary: On-site, Secondary: Online) |
A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50 |
[more] |
VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50 pp.49-54 |
CPSY, DC, IPSJ-ARC [detail] |
2022-07-27 10:15 |
Yamaguchi |
Kaikyo Messe Shimonoseki (Yamaguchi, Online) (Primary: On-site, Secondary: Online) |
On the Acceleration of a Low Power Oriented Test Generation Method Using Fault Excitation Conditions Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) CPSY2022-2 DC2022-2 |
[more] |
CPSY2022-2 DC2022-2 pp.7-12 |
CPSY, DC, IPSJ-ARC [detail] |
2022-07-27 11:00 |
Yamaguchi |
Kaikyo Messe Shimonoseki (Yamaguchi, Online) (Primary: On-site, Secondary: Online) |
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3 |
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] |
CPSY2022-3 DC2022-3 pp.13-18 |
CPSY, DC, IPSJ-ARC [detail] |
2022-07-27 11:30 |
Yamaguchi |
Kaikyo Messe Shimonoseki (Yamaguchi, Online) (Primary: On-site, Secondary: Online) |
An Evaluation of Field Testability Using States Signal Sequences Based on k-Consecutive State Transitions for Field Testing Yudai Toyooka, Yuki Watanabe, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2022-4 DC2022-4 |
[more] |
CPSY2022-4 DC2022-4 pp.19-24 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2022-03-10 10:30 |
Online |
Online (Online) |
A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90 |
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] |
CPSY2021-56 DC2021-90 pp.67-72 |
DC |
2022-03-01 13:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo, Online) (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on SFLL-hd at Register Transfer Level Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72 |
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] |
DC2021-72 pp.45-50 |
DC |
2022-03-01 15:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo, Online) (Primary: On-site, Secondary: Online) |
State assignment method to improve transition fault coverage for controllers including invalid states Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) DC2021-75 |
[more] |
DC2021-75 pp.63-68 |