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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-28
14:30
Okinawa Okinawa Ken Seinen Kaikan [Memorial Lecture] Towards Practical Homomorphic Email Filtering: A Hardware-Accelerated Secure Naive Bayesian Filter
Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2018-115 HWS2018-78
 [more] VLD2018-115 HWS2018-78
pp.133-138
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
09:50
Hiroshima Satellite Campus Hiroshima A study on estimating the degradation of critical path delay using replica sensors
Kunihiro Oshima, Son Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2018-67 DC2018-53
In this paper, we propose a novel method to estimate the aging-induced timing degradation of logic circuits. In the prop... [more] VLD2018-67 DC2018-53
pp.195-200
CAS, SIP, MSS, VLD 2018-06-14
16:35
Hokkaido Hokkaido Univ. (Frontier Research in Applied Sciences Build.) Area Efficient Multiply-Accumulate Circuit Using Stochastic Computing for Neural Network Hardware
Kenta Nagura, Masayuki Hiromoto, Takashi Sato (Kyoto Univ) CAS2018-15 VLD2018-18 SIP2018-35 MSS2018-15
Neural network, which is an accurate and general-purpose machine learning method, is attracting greater attention in rec... [more] CAS2018-15 VLD2018-18 SIP2018-35 MSS2018-15
pp.81-86
SDM 2017-11-09
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Characterization and modeling of SiC power MOSFET
Takashi Sato, Kazuki Oishi, Masayuki Hiromoto (Kyoto Univ.), Michihiro Shintani (NAIST) SDM2017-65
(To be available after the conference date) [more] SDM2017-65
pp.21-26
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:50
Kumamoto Kumamoto-Kenminkouryukan Parea A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit
Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2017-40 DC2017-46
Studies on physical unclonable function (PUF) have been actively conducted as one of the countermeasures against counter... [more] VLD2017-40 DC2017-46
pp.79-84
SIS 2017-03-03
09:50
Kanagawa Kanagawa Inst. Tech. Yokohama Office A Fast Reconstruction Method for Compressed Sensing of Videos Utilizing Inter-frame Correlation
Satoshi Konishi, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) SIS2016-55
Compressed sensing saves the cost of information acquisition at the expense of large computational efforts for the recon... [more] SIS2016-55
pp.77-82
VLD 2016-03-02
09:25
Okinawa Okinawa Seinen Kaikan An FPGA Implementation of Fast 2D-Ising-Model Solver for the Max-Cut Problem
Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2015-133
Ising-model-based solver attracts increasing attention as an excellent candidate for solving the combinatorial optimizat... [more] VLD2015-133
pp.125-130
VLD 2015-03-03
08:50
Okinawa Okinawa Seinen Kaikan A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture
Song Bian, Michihiro Shintani (Kyoto Univ.), Zheng Wang (RWTH Aachen Univ.), Masayuki Hiromoto (Kyoto Univ.), Anupam Chattopadhyay (Nanyang Tech. Univ.), Takashi Sato (Kyoto Univ.) VLD2014-161
 [more] VLD2014-161
pp.49-54
VLD 2015-03-04
08:50
Okinawa Okinawa Seinen Kaikan Physical Unclonable Function Using RTN-Induced Time-Dependent Frequency Variance in Ring Oscillator
Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2014-174
(To be available after the conference date) [more] VLD2014-174
pp.117-122
EMCJ, WPT
(Joint)
2015-01-23
16:15
Okinawa Okinawaken Jichikaikan Rational Function Approximation of Frequency Response and Equivalent Circuit Model for Three-Terminal Capacitor
Yuto Takagaki (Kyoto Univ.), Hiroshi Mifune, Seiji Hidaka (Murata Manufacturing Co., Ltd.), Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) EMCJ2014-101
This paper describes a method to model the equivalent circuit of a three-terminal capacitor for broadband frequency resp... [more] EMCJ2014-101
pp.89-94
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:35
Oita B-ConPlaza An efficient calculation of RTN-induced SRAM failure probability
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2014-74 DC2014-28
Failure rate degradation of an SRAM cell due to random telegraph noise (RTN) is calculated for the first time. An effic... [more] VLD2014-74 DC2014-28
pp.15-20
ICD, ITE-IST 2013-07-05
17:40
Hokkaido San Refre Hakodate Failure mode analysis for flip-flops at low voltages
Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto (Kyouto Univ.), Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Sato (Kyouto Univ.) ICD2013-45
Towards the reducing power consumption, subthreshold circuit which operates at a low voltage below the threshold voltage... [more] ICD2013-45
pp.129-134
VLD, IPSJ-SLDM 2010-05-19
17:00
Fukuoka Kitakyushu International Conference Center Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture
Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-4
Advancing CMOS process technology implies decreasing operating voltages, leaving LSI increasingly vulnerable to temporar... [more] VLD2010-4
pp.37-42
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-28
09:50
Kagoshima   An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA
Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) DC2007-105 CPSY2007-101
Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-... [more] DC2007-105 CPSY2007-101
pp.127-132
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
14:10
Kanagawa Hiyoshi Campus, Keio University A Tile Based Dynamically Reconfigurable Architecture with Dual ALU-array/RISC Processor Operating Mode Capability
Shin'ichi Kouyama, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) VLD2007-128 CPSY2007-71 RECONF2007-74
 [more] VLD2007-128 CPSY2007-71 RECONF2007-74
pp.59-64
VLD, IPSJ-SLDM 2007-05-11
10:55
Kyoto Kyodai Kaikan An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA
Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) VLD2007-10
Synchronous design methodology is widely used for today's digital circuits. However, highly optimized synchronous design... [more] VLD2007-10
pp.19-24
RECONF 2006-05-18
11:30
Miyagi TOHOKU UNIVERSITY A Retargetable Compiler for Cell-Array Based Self-Reconfigurable Architecture
Masayuki Hiromoto, Shin'ichi Kouyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.)
Simulation-based quantitative performance evaluation using specific applications is indispensable for developing archite... [more] RECONF2006-2
pp.7-12
 Results 1 - 17 of 17  /   
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