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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-02-28 14:50 |
Okinawa | (Okinawa, Online) (Primary: On-site, Secondary: Online) |
High Level Datapath Synthesis for Enhanced Timing Tunability Mineo Kaneko (JAIST)  VLD2023-101 HWS2023-61 ICD2023-90 |
[more] | VLD2023-101 HWS2023-61 ICD2023-90 pp.12-17 |
| HWS, VLD | 2023-03-02 11:25 |
Okinawa | (Okinawa, Online) (Primary: On-site, Secondary: Online) |
Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution Mineo Kaneko (JAIST) VLD2022-89 HWS2022-60 |
[more] | VLD2022-89 HWS2022-60 pp.97-102 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 13:30 |
Kumamoto | (Kumamoto, Online) (Primary: On-site, Secondary: Online) |
A Study on Co-Optimization of logical structure and bit-line placement for Parallel Prefix Adders Mineo Kaneko (JAIST) VLD2022-20 ICD2022-37 DC2022-36 RECONF2022-43 |
[more] | VLD2022-20 ICD2022-37 DC2022-36 RECONF2022-43 pp.7-12 |
| VLD, HWS [detail] | 2022-03-07 10:25 |
Online | Online (Online) | Datapath Synthesis Considering Temperature Dependent Timing Skew Mineo Kaneko (JAIST) VLD2021-79 HWS2021-56 |
[more] | VLD2021-79 HWS2021-56 pp.19-24 |
| HWS, VLD [detail] | 2021-03-04 10:20 |
Online | Online (Online) | A Fundamental Study on Three-Dimensional Module Placement for Layered Three-Dimensional LSI Tomohiro Noguchi, Hindawi Omran, Mineo Kaneko (JAIST) VLD2020-81 HWS2020-56 |
[more] | VLD2020-81 HWS2020-56 pp.73-78 |
| CAS, CS | 2021-03-01 15:50 |
Online | Online (Online) | [Fellow Memorial Lecture]
Fighting Against Variations for High Performance LSI: Mechanisms and Optimizations Mineo Kaneko (JAIST) CAS2020-76 CS2020-83 |
[more] | CAS2020-76 CS2020-83 pp.23-28 |
| NS, IN (Joint) |
2020-03-05 09:50 |
Okinawa | Royal Hotel Okinawa Zanpa-Misaki (Okinawa) (Cancelled but technical report was issued) |
Power Flow Management: A review of Models, and Issues Saher Javaid, Mineo Kaneko, Yasuo Tan, Yuto Lim (JAIST) IN2019-82 |
[more] | IN2019-82 pp.37-41 |
| HWS, VLD [detail] | 2020-03-04 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan (Okinawa) (Cancelled but technical report was issued) |
Thermal-Aware Clock Skew Scheduling Based on Two-Graph Approach Mineo Kaneko (JAIST) VLD2019-104 HWS2019-77 |
[more] | VLD2019-104 HWS2019-77 pp.59-64 |
| CAS, MSS, IPSJ-AL [detail] | 2019-11-28 13:00 |
Fukuoka | (Fukuoka) | Optimization of Parallel Prefix Adder Structure Generated by Insertion Operations Mineo Kaneko (JAIST) CAS2019-48 MSS2019-27 |
[more] | CAS2019-48 MSS2019-27 pp.21-26 |
| HWS, VLD | 2019-02-27 12:40 |
Okinawa | Okinawa Ken Seinen Kaikan (Okinawa) | Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2018-96 HWS2018-59 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2018-96 HWS2018-59 pp.19-24 |
| HWS, VLD | 2019-02-27 15:45 |
Okinawa | Okinawa Ken Seinen Kaikan (Okinawa) | Timing Correction by Constrained Temperature Dependent Clock Skew Mineo Kaneko (JAIST) VLD2018-103 HWS2018-66 |
This report treats temperature dependent clock skew scheduling for a general class of sequential circuits. Previous stud... [more] | VLD2018-103 HWS2018-66 pp.61-66 |
| VLD, HWS (Joint) |
2018-02-28 13:55 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Congestion Aware High Level Synthesis Design Flow with Source Compiler Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2017-96 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2017-96 pp.43-48 |
| VLD, HWS (Joint) |
2018-02-28 16:30 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults Cheng Ma, Mineo Kaneko (JAIST) VLD2017-101 |
The report treats the reconfiguration-based fault-tolerance for FPGA applications, and proposes a method of finding a ch... [more] | VLD2017-101 pp.73-78 |
| VLD, HWS (Joint) |
2018-02-28 16:55 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2017-102 |
Among several problems with miniaturization of LSIs, soft-errors are one of serious problems to make reliability worse. ... [more] | VLD2017-102 pp.79-84 |
| VLD, HWS (Joint) |
2018-03-01 11:20 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | VLD2017-109 |
[more] | VLD2017-109 pp.121-126 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea (Kumamoto) | A General Model of Timing Correction by Temperature Dependent Clock Skew Mineo Kaneko (JAIST) VLD2017-57 DC2017-63 |
[more] | VLD2017-57 DC2017-63 pp.183-188 |
| VLD | 2017-03-02 15:00 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118 |
The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order t... [more] | VLD2016-118 pp.85-90 |
| VLD | 2017-03-02 15:25 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Optimum Temperature Dependent Timing Skew for Temperature Aware Design Makoto Soga, Mineo Kaneko (JAIST) VLD2016-119 |
Electric devices equipping LSIs are widely distributed everywhere on the earth and the space, and LSIs are demanded to o... [more] | VLD2016-119 pp.91-96 |
| VLD | 2017-03-02 15:50 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | MILP Approach to Skew-Aware High Level Synthesis Kai Shimura, Mineo Kaneko (JAIST) VLD2016-120 |
Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed. However, when we tr... [more] |
VLD2016-120 pp.97-102 |
| VLD | 2017-03-03 11:20 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Optimization of Parallel Prefix Adder Using Simulated Annealing Takayuki Moto, Mineo Kaneko (JAIST) VLD2016-127 |
In this report, simulated annealing based optimization of parallel prefix adders (PPA) is proposed. In order to construc... [more] | VLD2016-127 pp.139-144 |
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