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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2016-01-28
15:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme
Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] SDM2015-126
pp.27-30
ICD 2015-04-17
12:40
Nagano   [Invited Talk] Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10
 [more] ICD2015-10
pp.45-50
SDM 2015-01-27
14:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques
Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] SDM2014-142
pp.29-32
ICD 2010-04-22
13:30
Kanagawa Shonan Institute of Tech. [Invited Talk] A 64Mbit MRAM with Clamped-Reference and Adequate-Reference Schemes
Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe (TOSHIBA) ICD2010-7
A 64Mb spin-transfer-torque MRAM in 65nm CMOS is developed. 47mm2 die uses 0.3584um2 cell with the perpendicular-TMR dev... [more] ICD2010-7
pp.35-40
MRIS, ITE-MMS 2008-12-11
16:50
Ehime Ehime University [Invited Talk] Excellent scalability of Magnetic Random Access Memory using spin transfer switching and perpendicular magnetic anisotropy
Masahiko Nakayama, Tadashi Kai, Hisanori Aikawa, Junichi Ozeki, Katsuya Nishiyama, Toshihiko Nagase, Minoru Amano, Sumio Ikegawa, Tatsuya Kishi, Hiroaki Yoda (Toshiba) MR2008-44
Low switching current and Large thermal stability factor is important for achieving a high-density MRAM using spin trans... [more] MR2008-44
pp.37-41
ICD 2008-04-18
14:45
Tokyo   Experimental proof of spin transfer switching in MRAM cell using TbCoFe/CoFeB layers with perpendicular magnetic anisotropy
Masahiko Nakayama, Tadashi Kai, Naoharu Shimomura, Minoru Amano, Eiji Kitagawa, Toshihiko Nagase, Masatoshi Yoshikawa, Tatsuya Kishi, Sumio Ikegawa, Hiroaki Yoda (R&D Center, Toshiba Corp.) ICD2008-14
(To be available after the conference date) [more] ICD2008-14
pp.75-78
 Results 1 - 6 of 6  /   
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