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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, HWS [detail] 2020-10-26
09:25
Online Online Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware
Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2020-26 ICD2020-15
To reduce the latency of pairing calculation for advanced cryptography, hardware implementations with pipelined modular ... [more] HWS2020-26 ICD2020-15
pp.7-12
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
14:25
Kochi Kochi University of Technology Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier
Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
pp.151-156
HWS
(2nd)
2018-12-13
16:10
Tokyo Tokyo Univ. Takeda Bldg. Takeda Hall [Poster Presentation] Side-channel Attack using Average Power Traces against Pairing Implementation with Random Masking Countermeasure
Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU)
(Advance abstract in Japanese is available) [more]
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