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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, ITE-IST 2010-07-22
15:50
Osaka Josho Gakuen Osaka Center [Invited Talk] A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter
Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.) ICD2010-29
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital conver... [more] ICD2010-29
pp.49-54
ICD, SDM 2006-08-17
15:10
Hokkaido Hokkaido University Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link
Mari Inoue, Noriyuki Miura, Kiichi Niitsu (Keio Univ.), Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi (NEC Corp.), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.)
 [more] SDM2006-136 ICD2006-90
pp.63-68
ICD 2006-05-26
15:45
Hyogo Kobe University A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu (Keio Univ.), Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi (NEC), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.)
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate o... [more] ICD2006-38
pp.95-100
ICD 2005-05-27
11:00
Hyogo Kobe Univ. 12Gb/s duobinary signaling with x2 oversampled edge equalization
Kouichi Yamaguchi, Kazuhisa Sunaga, Shunichi Kaeriyama, Takaaki Nedachi, Makoto Takamiya, Koichi Nose, Yoshihiro Nakagawa (NEC), Mitsutoshi Sugawara (NEC-EL America), Muneo Fukaishi (NEC)
A backplane transceiver in 90nm CMOS that employs duobinary signaling over copper traces is described. To introduce duob... [more] ICD2005-30
pp.13-18
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